Patents by Inventor HEE-WOONG KANG
HEE-WOONG KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961559Abstract: A storage device includes a nonvolatile memory device and a memory controller allowing the nonvolatile memory device to perform a read operation on memory cells belonging to a selected page in a selected memory block. After the read operation, the memory controller allows the nonvolatile memory device to perform a first check read operation on memory cells of a first neighbor page while sequentially selecting sets of read voltages. After the first check read operation, the memory controller allows the nonvolatile memory device to perform a second check read operation on memory cells of a second neighbor page while sequentially selecting the sets of read voltages. In the second check read operation, the memory controller first selects a set of read voltages, which are used in the first check read operation in which error correction succeeds.Type: GrantFiled: June 2, 2022Date of Patent: April 16, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Yunjung Lee, Hee-Woong Kang
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Patent number: 11942140Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.Type: GrantFiled: October 1, 2022Date of Patent: March 26, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hee-Woong Kang, Dong-Hun Kwak, Jun-Ho Seo, Hee-Won Lee
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Patent number: 11799497Abstract: A method for operating a storage controller includes receiving a first read command, performing a first read of data stored in a nonvolatile memory using a first read level and receiving a first read data, performing first error correction decoding of the first read data to determine whether the first error correction decoding succeeds, determining a second read level using a predetermined method, and determining a first soft decision offset value of the second read level, reading data stored in the nonvolatile memory using the determined second read level and the first soft decision offset value and receiving a first soft decision data, performing second error correction decoding of the first soft decision data to determine whether the second error correction decoding succeeds, and storing the second read level, a first method used to determine the second read level and the first soft decision offset value.Type: GrantFiled: May 14, 2022Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong Woo Lee, Sang Jin Yoo, Hee-Woong Kang, Kwang Woo Lee, Hee Won Lee
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Publication number: 20230142506Abstract: A storage device includes a nonvolatile memory device and a memory controller allowing the nonvolatile memory device to perform a read operation on memory cells belonging to a selected page in a selected memory block. After the read operation, the memory controller allows the nonvolatile memory device to perform a first check read operation on memory cells of a first neighbor page while sequentially selecting sets of read voltages. After the first check read operation, the memory controller allows the nonvolatile memory device to perform a second check read operation on memory cells of a second neighbor page while sequentially selecting the sets of read voltages. In the second check read operation, the memory controller first selects a set of read voltages, which are used in the first check read operation in which error correction succeeds.Type: ApplicationFiled: June 2, 2022Publication date: May 11, 2023Inventors: YUNJUNG LEE, HEE-WOONG KANG
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Publication number: 20230064060Abstract: A method for operating a storage controller includes receiving a first read command, performing a first read of data stored in a nonvolatile memory using a first read level and receiving a first read data, performing first error correction decoding of the first read data to determine whether the first error correction decoding succeeds, determining a second read level using a predetermined method, and determining a first soft decision offset value of the second read level, reading data stored in the nonvolatile memory using the determined second read level and the first soft decision offset value and receiving a first soft decision data, performing second error correction decoding of the first soft decision data to determine whether the second error correction decoding succeeds, and storing the second read level, a first method used to determine the second read level and the first soft decision offset value.Type: ApplicationFiled: May 14, 2022Publication date: March 2, 2023Inventors: Jeong Woo LEE, Sang Jin YOO, Hee-Woong KANG, Kwang Woo LEE, Hee Won LEE
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Publication number: 20230036205Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.Type: ApplicationFiled: October 1, 2022Publication date: February 2, 2023Inventors: Hee-Woong KANG, Dong-Hun KWAK, Jun-Ho SEO, Hee-Won LEE
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Patent number: 11462260Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.Type: GrantFiled: May 14, 2021Date of Patent: October 4, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hee-Woong Kang, Dong-Hun Kwak, Jun-Ho Seo, Hee-Won Lee
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Publication number: 20210272617Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.Type: ApplicationFiled: May 14, 2021Publication date: September 2, 2021Inventors: Hee-Woong KANG, Dong-Hun KWAK, Jun-Ho SEO, Hee-Won LEE
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Patent number: 11017838Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.Type: GrantFiled: August 12, 2020Date of Patent: May 25, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hee-Woong Kang, Dong-Hun Kwak, Jun-Ho Seo, Hee-Won Lee
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Publication number: 20200372945Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.Type: ApplicationFiled: August 12, 2020Publication date: November 26, 2020Inventors: Hee-Woong KANG, Dong-Hun KWAK, Jun-Ho SEO, Hee-Won LEE
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Patent number: 10777254Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: GrantFiled: March 13, 2020Date of Patent: September 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hun Kwak, Hee-Woong Kang, Jun-Ho Seo, Hee-Won Lee
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Publication number: 20200219552Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: ApplicationFiled: March 13, 2020Publication date: July 9, 2020Inventors: Dong-Hun KWAK, Hee-Woong KANG, Jun-Ho SEO, Hee-Won LEE
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Patent number: 10672454Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: GrantFiled: November 6, 2019Date of Patent: June 2, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hun Kwak, Hee-Woong Kang, Jun-Ho Seo, Hee-Won Lee
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Patent number: 10629254Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: GrantFiled: November 7, 2018Date of Patent: April 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hun Kwak, Hee-Woong Kang, Jun-Ho Seo, Hee-Won Lee
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Publication number: 20200075078Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: ApplicationFiled: November 6, 2019Publication date: March 5, 2020Inventors: Dong-Hun KWAK, Hee-Woong KANG, Jun-Ho SEO, Hee-Won LEE
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Patent number: 10445010Abstract: In a method of throttling temperature of a nonvolatile memory device including a memory cell array, a current temperature of the nonvolatile memory device may be detected periodically. The current temperature may be compared with a reference temperature. Whether an external input/output command, which is provided by a memory controller, exists may be determined when the current temperature is lower than the reference temperature. An input/output operation, which corresponds to the external input/output command, may be performed on the memory cell array when the external input/output command exists. A desired and/or alternatively predetermined internal input/output operation may be performed on the memory cell array regardless of a command from the memory controller when the external input/output command does not exist.Type: GrantFiled: February 23, 2017Date of Patent: October 15, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Won Jeong, Hee-Woong Kang
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Publication number: 20190074048Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: ApplicationFiled: November 7, 2018Publication date: March 7, 2019Inventors: Dong-Hun KWAK, Hee-Woong KANG, Jun-Ho SEO, Hee-Won LEE
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Patent number: 10153029Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.Type: GrantFiled: May 24, 2017Date of Patent: December 11, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Hun Kwak, Hee-Woong Kang, Jun-Ho Seo, Hee-Won Lee
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Patent number: 10008272Abstract: A nonvolatile memory system includes a nonvolatile memory device and a memory controller that controls the nonvolatile memory device. The nonvolatile memory device includes multiple memory blocks. Each of the memory blocks includes memory cells. Each of the memory cells has any one of an erase state and one of multiple different program states. An operation method of the nonvolatile memory system includes receiving a physical erase command from an external device. The operation method also includes performing a fast erase operation, responsive to the received physical erase command, with respect to at least one memory block so that first memory cells of the at least one memory block have a fast erase state different from the erase state.Type: GrantFiled: May 5, 2017Date of Patent: June 26, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Woong Kang, Donghun Kwak, Daeseok Byeon, Ju Seok Lee
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Publication number: 20180067678Abstract: In a method of throttling temperature of a nonvolatile memory device including a memory cell array, a current temperature of the nonvolatile memory device may be detected periodically. The current temperature may be compared with a reference temperature. Whether an external input/output command, which is provided by a memory controller, exists may be determined when the current temperature is lower than the reference temperature. An input/output operation, which corresponds to the external input/output command, may be performed on the memory cell array when the external input/output command exists. A desired and/or alternatively predetermined internal input/output operation may be performed on the memory cell array regardless of a command from the memory controller when the external input/output command does not exist.Type: ApplicationFiled: February 23, 2017Publication date: March 8, 2018Inventors: Sung-Won JEONG, Hee-Woong KANG