Abstract: The present invention relates to a method for preparing terephthalic acid, and terephthalic acid prepared therefrom. Specifically, according to one embodiment of the present invention, by including the step of hydrolyzing a compound prepared by depolymerizing a waste polyester using a specific hydrolysis catalyst, terephthalic acid can be prepared in an environmentally friendly manner, and high purity terephthalic acid can be provided.

Abstract: The present invention pertains to a method for producing terephthalic acid in an eco-friendly manner using waste polyester. Specifically, according to an embodiment of the present invention, the method for producing terephthalic acid comprises the steps of: (1) subjecting waste polyester to alcoholysis using a C4 or higher alcohol to produce a liquid composition containing a compound represented by formula 1; and (2) subjecting the liquid composition to hydrolysis, and thus can produce terephthalic acid in an eco-friendly manner, as well as improve processability and reduce process costs.

Abstract: The present invention relates to a method for preparing terephthalic acid, and terephthalic acid prepared therefrom. Specifically, according to one embodiment of the present invention, by including the step of hydrolyzing a compound prepared by depolymerizing a waste polyester using a specific hydrolysis catalyst, terephthalic acid can be prepared in an environmentally friendly manner, and high purity terephthalic acid can be provided.

Abstract: A method for cycloaddition of dimethyl muconate is disclosed. According to the method, a direct transferring of a solid phase trans,trans-dimehtyl muconate into a reactor pre-filled with ethylene gas increases the efficiency of the reaction and suppress side reactions resulting an improvements in yield and purity. Furthermore, the method is capable of obtaining a high yield of dimethylcyclohex-2-en-1,4-dicarboxylate at a lower cost, and therefore is also useful for the mass synthesis of dimethyl terephthalate.

Abstract: A method for cycloaddition of dimethyl muconate is disclosed. According to the method, a direct transferring of a solid phase trans,trans-dimehtyl muconate into a reactor pre-filled with ethylene gas increases the efficiency of the reaction and suppress side reactions resulting an improvements in yield and purity. Furthermore, the method is capable of obtaining a high yield of dimethylcyclohex-2-en-1,4-dicarboxylate at a lower cost, and therefore is also useful for the mass synthesis of dimethyl terephthalate.

Abstract: In a DRAM device having a capacitor and a method thereof, the capacitor included in the device is characterized to have a lower electrode that passes through a plurality of interlayer insulating layers. A first interlayer insulating layer is formed on a semiconductor substrate. A first contact plug layer is formed through the first interlayer insulating to electrically contact the semiconductor substrate. An insulating layer is formed on the first interlayer insulating layer. The insulating layer is etched to form the first interlayer insulating layer and a temporary storage node hole exposing the first contact plug. The first interlayer insulating layer exposed by the temporary storage node hole and portions of the first contact plug are simultaneously etched to form a storage node hole. A lower electrode layer is conformally formed on a surface of the semiconductor substrate having the storage node hole.

Abstract: A semiconductor device includes a semiconductor layer disposed between a semiconductor substrate and a gate electrode, a back gate insulating layer pattern disposed between the semiconductor layer and the semiconductor substrate, and a gate insulating layer disposed between the semiconductor layer and the gate electrode. The semiconductor substrate extends from both sides of the back gate insulating layer pattern to the gate insulating layer and is directly in contact with a sidewall of the semiconductor layer.

Abstract: In a method of forming a DRAM device having a capacitor and a DRAM device so formed, an interlayer dielectric having at least one layer is formed on a semiconductor substrate. The interlayer dielectric layer and a predetermined portion of the semiconductor substrate are sequentially etched to form a storage node hole. A lower electrode is conformally formed in the storage node hole and on the interlayer dielectric layer. A planarization process is performed to remove a portion of the lower electrode layer that lies on the interlayer dielectric layer and to form a lower electrode in the storage node hole. A dielectric layer and an upper electrode layer are sequentially formed on the lower electrode. The upper electrode layer and the dielectric layer are sequentially patterned.

Abstract: A capacitor of a semiconductor device and a method for fabricating the same may be provided. The method may include forming an interlayer insulation layer, an etch stop layer, and/or a sacrificial insulation layer on a semiconductor substrate, patterning the interlayer insulation layer, the etch stop layer, and/or the sacrificial insulation layer to form a contact hole exposing a desired or predetermined region of the semiconductor substrate, filling the contact hole to form a contact plug, removing the sacrificial insulation layer to expose an upper portion of the contact plug, and/or forming a dielectric layer and/or a top electrode on the exposed upper portion of the contact plug.

Abstract: In a method of forming a DRAM device having a capacitor and a DRAM device so formed, an interlayer dielectric having at least one layer is formed on a semiconductor substrate. The interlayer dielectric layer and a predetermined portion of the semiconductor substrate are sequentially etched to form a storage node hole. A lower electrode is conformally formed in the storage node hole and on the interlayer dielectric layer. A planarization process is performed to remove a portion of the lower electrode layer that lies on the interlayer dielectric layer and to form a lower electrode in the storage node hole. A dielectric layer and an upper electrode layer are sequentially formed on the lower electrode. The upper electrode layer and the dielectric layer are sequentially patterned.

Abstract: In a DRAM device having a capacitor and a method thereof, the capacitor included in the device is characterized to have a lower electrode that passes through a plurality of interlayer insulating layers. A first interlayer insulating layer is formed on a semiconductor substrate. A first contact plug layer is formed through the first interlayer insulating to electrically contact the semiconductor substrate. An insulating layer is formed on the first interlayer insulating layer. The insulating layer is etched to form the first interlayer insulating layer and a temporary storage node hole exposing the first contact plug. The first interlayer insulating layer exposed by the temporary storage node hole and portions of the first contact plug are simultaneously etched to form a storage node hole. A lower electrode layer is conformally formed on a surface of the semiconductor substrate having the storage node hole.

Abstract: A semiconductor device having a metal suicide layer and a method of manufacturing the same are provided. A spacer material layer is formed on a semiconductor substrate on which a gate and a source and drain region having a low impurity concentration are formed. Only the spacer material layer, which is formed in a region in which a silicide layer is to be formed, is etched. A source and drain region having a high impurity concentration is formed in the exposed semiconductor substrate, and a silicide layer is formed on the source and drain region having a high impurity concentration. Since an extra silicide blocking layer (SBL) is not formed, a photomask process of patterning a SBL is not performed. That is, one photolithographic process is reduced in comparison with a conventional process of selectively forming a silicide layer. Thus, a process of manufacturing a semiconductor device can be simplified, thereby reducing process costs and reducing the danger of misalignment occurring during a photomask process.