Abstract: A semiconductor device according to an example embodiment of the present disclosure may include: a lower channel pattern extending in a vertical direction; a lower gate electrode overlapping the lower channel pattern in a first horizontal direction; an upper channel pattern overlapping the lower channel pattern in the vertical direction; an upper gate electrode overlapping the upper channel pattern in the first horizontal direction; and a charge storage region extending in the vertical direction and contacting the upper channel pattern. The lower channel pattern may include a first source/drain region, a second source/drain region spaced apart from the first source/drain region in the vertical direction, and a channel region between the first source/drain region and the second source/drain region, and at least a portion of the charge storage region may overlap the lower channel pattern in a second horizontal direction, intersecting the first horizontal direction.

Abstract: A semiconductor device may include a substrate having a cell array region, a peripheral circuit region, and a connection region; a cell element separation pattern defining a cell active region on the cell array region; a peripheral element separation pattern defining a peripheral active region on the peripheral circuit region; a separation insulating pattern between the cell element separation pattern and the peripheral element separation pattern on the connection region; and a cell gate structure. A lower surface of the separation insulating pattern may include a first lower region adjacent to the peripheral circuit region and on a first level, a second lower region adjacent to the cell array region and on a second level that is higher than the first level relative to an upper surface of the substrate, and a first step portion between the first lower region and the second lower region.

Abstract: A semiconductor device includes a bit line on a substrate, a plate line on the substrate and spaced apart from the bit line in a first direction substantially parallel to an upper surface of the substrate facing the bit line, a first channel between the bit line and the plate line, a first word line wherein the first channel is between the first word line and the substrate and extending in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction, a second channel between the first channel and the substrate, a data storage pattern between the bit line and the plate line at a same distance from the substrate as the second channel, and a second word line between the second channel and the substrate and extending in the second direction.

Abstract: A semiconductor device includes a bit line extending in a vertical direction, and a 2-transistor (2T) memory cell including a first transistor and a second transistor on the first transistor. The first transistor includes an active pattern contacting the bit line, the active pattern including a first and second source/drain region, and a channel region, and a first gate structure including a first gate electrode layer overlapping the channel region. The second transistor includes a second gate structure including a second gate electrode layer, a channel structure contacting the bit line, the channel structure including a first horizontal portion extending in a first horizontal direction away from the bit line, and a vertical portion extending vertically from one end of the first horizontal portion, and a storage node between the first gate electrode layer and the second gate electrode layer, and the storage node connected to the channel structure.

Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a plurality of vertical channel transistors and a boundary region surrounding each of the plurality of memory cell blocks in a planar view. The semiconductor device includes a first device isolation layer facing the plurality of vertical channel transistors in a first horizontal direction in the boundary region and a second device isolation layer apart from the plurality of vertical channel transistors in the first horizontal direction with the first device isolation layer therebetween. The first device isolation layer includes a first portion, a second portion disposed on the first portion, and a step portion disposed on the first portion and extending from an inner wall of the second portion to the second device isolation layer in the first horizontal direction.

Abstract: A shock absorbing apparatus according to the present disclosure may comprise a block having a through hole vertically penetrating the block, and a first flow path, a second flow path, and a third flow path; and a first tube extending vertically through the through hole and having a penetration portion that penetrates an inner circumferential surface and an outer circumferential surface of the first tube so that an interior of the first tube is in fluid communication with the first flow path.

Abstract: A semiconductor device includes a bit line, a vertical active pattern on the bit line and extending lengthwise, a word line extending lengthwise in a first horizontal direction and overlapping the vertical active pattern in a second horizontal direction, a gate insulating pattern provided in a space between the word line and the vertical active pattern, an electric field generating pattern provided next to the vertical active pattern in the first and second horizontal directions, and a buffer layer located in a space between the vertical active pattern and the electric field generating pattern in the first and second horizontal directions. The electric field generating pattern has a strain gradient from an interface between the buffer layer and the electric field generating pattern toward an inside of the electric field generating pattern. The strain gradient induces an electric polarization in the electric field generating pattern.

Abstract: An example method of manufacturing a semiconductor device is provided in which, after a sacrificial layer is formed on a vertical channel pattern of a plurality of vertical channel patterns, a source layer is formed on a side of the vertical channel pattern, and a junction region is formed on the vertical channel pattern.

Abstract: A semiconductor device includes a peripheral circuit structure including a peripheral circuit pattern, a bonding structure including a bonding layer structure, a cell structure including a channel extending in a vertical direction perpendicular to an upper surface of a substrate, a word line at a side of the channel and extending in a first direction parallel to the upper surface of the substrate, a bit line structure at one end of the channel in the vertical direction and extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, and a capacitor at another end of the channel in the vertical direction and electrically connected thereto, a word line wiring structure electrically connecting the peripheral circuit pattern and the word line, and a bit line wiring structure electrically connecting the peripheral circuit pattern and the bit line structure.

Abstract: The semiconductor device include a bit line extending in a first direction, a first gate electrode extending on the bit line in a second direction, a first gate insulation pattern including a first portion covering each of opposite sidewalls in the first direction and the end portion in the second direction of the first gate electrode and a second portion contacting the first portion and extending in the second direction, a channel extending in a third direction, the channel being disposed on a side in the first direction of the first gate insulation pattern on the bit line and a second gate insulation pattern and a second gate electrode sequentially arranged in the first direction on a side in the first direction of the channel on the bit line. An end portion in the second direction of the first gate electrode has a central portion with respect to the first direction, and the end portion protrudes in the second direction in a plan view.

Abstract: A semiconductor device includes a bitline structure, a back gate structure disposed on the bitline structure, a word line structure disposed on the bitline structure, an active pattern disposed on the bitline structure and extending in a vertical direction between the back gate structure and the word line structure, a first insulating pattern contacting the active pattern, between the bitline structure and the back gate structure, a second insulating pattern contacting the active pattern, between the bitline structure and the word line structure, and a contact pattern on the active pattern. A horizontal width of the first insulating pattern is smaller than a horizontal width of the back gate structure. A horizontal width of the second insulating pattern is smaller than a horizontal width of the word line structure.

Abstract: A semiconductor device may include a semiconductor substrate including a horizontal portion and a vertical portion protruding upward from the horizontal portion, a bit line on the semiconductor substrate and extending in a first direction parallel to a bottom surface of the semiconductor substrate, a word line on the bit line and extending in a second direction parallel to the bottom surface of the semiconductor substrate that is different from the first direction, a semiconductor pattern on the vertical portion of the semiconductor substrate and extending in a third direction perpendicular to the bottom surface of the semiconductor substrate, and a metal silicide pattern between the semiconductor pattern and the bit line. The semiconductor pattern may include a source/drain region adjacent to the bit line and a channel region on the source/drain region, and the metal silicide pattern may be in contact with the source/drain region and the bit line.

Abstract: A semiconductor device includes a bitline structure, a first gate structure extending in a first horizontal direction on the bitline structure and including a first gate electrode, a second gate structure extending in the first horizontal direction on the bitline structure and including a second gate electrode, an active pattern including a portion being between the first gate structure and the second gate structure, and a contact pattern on the active pattern, wherein the active pattern is in contact with an upper surface of the bitline structure and in contact with side surfaces and a lower surface of the first gate structure.

Abstract: A semiconductor device includes a substrate, a bit line on the substrate extending in a first direction parallel to an upper surface of the substrate, a first semiconductor pattern and a second semiconductor pattern on the bit line, each extending in a second direction perpendicular to the upper surface of the substrate, and spaced apart from each other in the first direction, a word line between the first semiconductor pattern and the second semiconductor pattern extending in the second direction, a first connection structure on one end portion of the first semiconductor pattern, a second connection structure on one end portion of the second semiconductor pattern, a data storage pattern on each of the first connection structure and the second connection structure, and a gap between the first connection structure and the second connection structure.

Abstract: A semiconductor device includes a bit line structure, a back gate structure extending on the bit line structure in a first horizontal direction, the back gate structure including a back gate electrode and an upper capping layer on the back gate electrode, a word line structure disposed on the bit line structure, the word line structure including a word line and a gate dielectric layer covering a side surface of the word line, an active pattern disposed on the bit line structure, the active pattern extending in a vertical direction between the back gate structure and the word line structure, and a contact pattern on the active pattern. The upper capping layer includes a seam extending in the first horizontal direction.

Abstract: A method of manufacturing a semiconductor device includes: forming an insulating layer on a substrate; forming mask patterns on the insulating layer, the mask patterns extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; forming spacer layers on side surfaces of the mask patterns, wherein the spacer layers are spaced apart from each other in the second horizontal direction with each of the mask patterns interposed therebetween; forming spacer patterns spaced apart from each other in the first horizontal direction on the side surfaces of the mask patterns by patterning the spacer layers; forming mold patterns by etching the insulating layer using the mask patterns and the spacer patterns as an etching mask; and forming a device isolation trench defining semiconductor patterns by etching the substrate using the mold patterns as an etching mask.

Abstract: A semiconductor device includes a plurality of active regions disposed at a substrate, a device isolation layer disposed at the substrate and surrounding each of the plurality of active regions, a supporter pattern surrounded by the device isolation layer and disposed in a space between two active regions of the plurality of active regions, a cell gate structure intersecting the plurality of active regions, the cell gate structure including a gate dielectric layer, a gate electrode on the gate dielectric layer, and a gate capping layer on the gate electrode, and a bit line structure intersecting one of the plurality of active regions and the cell gate structure. A lower surface of the supporter pattern is in contact with the device isolation layer, and an upper surface of the supporter pattern is in contact with the gate electrode.

Abstract: A semiconductor device includes first and second active patterns adjacent to each other in a first direction, each of the first and second active patterns including first and second edge portions spaced apart from each other, a word line crossing between the first and second edge portions of each of the first and second active patterns and extending in a wave shape in the first direction, a bit line on the first edge portion of the first active pattern, and a storage node contact on the second edge portion of the first active pattern, wherein the first active pattern extends in a second direction intersecting the first direction, and the second active pattern extends in a third direction that is symmetrical to the second direction with respect to the first direction.

Abstract: Provided is a semiconductor memory device including a semiconductor substrate, a plurality of memory active regions each having a long axis and a short axis, and arranged to maintain a first distance between memory active regions along the short axis and maintain a second distance between memory active regions along the long axis, a plurality of logic active regions each including at least a P-channel metal oxide semiconductor transistor and arranged to maintain a third distance therebetween, a first device isolation insulating layer in the first trench with a first portion that corresponds to a region between the memory active regions other along the direction of the long axis including a first nitride insulating layer, and a second device isolation insulating layer in the second trench between the logic active regions and that does not include the first nitride insulating layer, wherein the second distance is substantially the same as the third distance.

Abstract: A semiconductor device may include a plurality of active patterns disposed on a substrate, a gate structure extending in a first direction, a bit line structure extending in a second direction, and a plurality of capacitors electrically connected to the plurality of active patterns, respectively, the plurality of active patterns having a shape extending in a third direction oblique to the first and second directions, the gate structure passing through centers of the plurality of active patterns, the bit line structure connected to first end portions of the plurality of active patterns, the plurality of capacitors connected to second end portions of the plurality of active patterns, respectively, the first end portion and the second end portion positioned at opposite sides with respect to the gate structure, and the first end portion and the second end portion having point-symmetrical shapes with respect to a center of the active pattern.