Patents by Inventor Hee-Joo Choi
Hee-Joo Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240104464Abstract: A system selecting a process key factor in a commercial chemical process, includes: a data extraction unit that extracts tag data in units of a set period; an outlier discrimination unit that discriminates and aggregates outliers by tag by using an outlier extraction reference master; an outlier processing unit that generates an input mart draft excluding the outliers; a derived variable generation unit that generates derived variables for each tag, and generates an advanced input mart having the derived variable added thereto; a yield calculation unit that backs up the result of calculation of a yield by realizing a target value via exclusion and correction of the outliers; and a key factor extraction unit that extracts a yield key factor by calculating importance of each tag, and backs up importance data for each tag.Type: ApplicationFiled: April 27, 2022Publication date: March 28, 2024Applicant: SK GAS CO., LTD.Inventors: Ung Gi HONG, Sung Joo YEO, Seung Hwan KONG, Min Ho KIM, Hae Bin SHIN, Hee Dong CHOI, Young Gook KYE
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SYSTEM AND METHOD FOR PREDICTING PROCESS CHANGES BY USING KEY FACTORS IN COMMERCIAL CHEMICAL PROCESS
Publication number: 20240095548Abstract: A system for predicting process changes by using key factors in a commercial chemical process, includes: a key factor extraction and individual tag importance backup unit that extracts yield key factors by calculating the importance of each tag, and backs up importance data for each tag; and a yield prediction model training and yield prediction performing unit that performs yield prediction model training by using the importance of each tag accumulated in the key factor extraction and individual tag importance backup unit, and performs yield prediction so as to output a yield prediction result, evaluates performance, and selects an optimal prediction model.Type: ApplicationFiled: April 27, 2022Publication date: March 21, 2024Applicant: SK GAS CO., LTD.Inventors: Ung Gi HONG, Sung Joo YEO, Seung Hwan KONG, Min Ho KIM, Hae Bin SHIN, Hee Dong CHOI, Young Gook KYE -
Publication number: 20240090328Abstract: The present invention relates to a multi-component host material and an organic electroluminescent device comprising the same. By comprising a specific combination of the multi-component host compounds, the organic electroluminescent device according to the present invention can provide high luminous efficiency and excellent lifespan characteristics.Type: ApplicationFiled: October 26, 2023Publication date: March 14, 2024Inventors: Hee-Choon AHN, Young-Kwang KIM, Su-Hyun LEE, Ji-Song JUN, Seon-Woo LEE, Chi-Sik KIM, Kyoung-Jin PARK, Nam-Kyun KIM, Kyung-Hoon CHOI, Jae-Hoon SHIM, Young-Jun CHO, Kyung-Joo LEE
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Publication number: 20240082345Abstract: Provided is a peptide composition for preventing or treating Alzheimer's dementia. A peptide or a salt substituent thereof according to the presently claimed subject matter exhibits effects such as suppression of LPS-mediated cytokine production, suppression of LPS-induced neuroinflammation, amelioration of cognitive impairment, suppression of beta amyloid or tau protein aggregation, and suppression of neuronal loss. The polypeptide or the salt substituent thereof can permeate the blood-brain barrier, and thus, is expected to be usefully used for preventing or treating Alzheimer's dementia.Type: ApplicationFiled: August 25, 2021Publication date: March 14, 2024Applicant: HLB SCIENCE INC.Inventors: Yeong Min PARK, Wahn Soo CHOI, Seung-Hyun LEE, In Duk JUNG, Yong Joo KIM, Seung Jun LEE, Sung Min KIM, Mi Suk LEE, Hee Jo PARK, Seung Pyo CHOI, Minho MOON, Soo Jung SHIN, Sujin KIM, Yong Ho PARK, Jae-Yong PARK, Kun Ho LEE
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Publication number: 20200248271Abstract: A function of cyclin-dependent kinase 12 (CDK12) as a biomarker for a human epidermal growth factor receptor 2 (HER2)-positive cancer and anti-HER2 therapy, and a use of the CDK12 are provided. The CDK12 may be used for companion diagnostics of a HER2-targeted therapeutic agent for a subject having HER2+ cancer as a prognostic factor and a predictive factor for response of the subject to the anti-HER2-targeted therapeutic agent in HER2+ cancer, or used to check the probability of expressing resistance to the HER2-targeted therapeutic agent. When the CDK12 is amplified or expressed at a level higher than a reference value, the CDK12 may be suppressed to overcome the resistance to the HER2 therapeutic agent and improve a therapeutic effect, thereby improving the therapeutic efficiency of HER2-positive cancer.Type: ApplicationFiled: January 31, 2020Publication date: August 6, 2020Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITYInventors: Gu KONG, Jeong Yeon LEE, Hee-Joo CHOI, Ha Ni JO
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Patent number: 10083764Abstract: A memory system includes a memory controller, a memory cell array, a location information storage unit, an address mapping table, an address conversion unit, and a mapping information calculation unit. The memory controller generates a logical address signal and an address re-mapping command. The memory cell array includes a plurality of logic blocks. The location information storage unit stores location information corresponding to faulty memory cells included in the memory cell array. The address mapping table stores address mapping information. The address conversion unit converts the logical address signal to a physical address signal corresponding to the memory cell array based on the address mapping information. The mapping information calculation unit generates the address mapping information to reduce the number of logic blocks including the faulty memory cells based on the location information upon the mapping information calculation unit receiving the address re-mapping command.Type: GrantFiled: October 27, 2014Date of Patent: September 25, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mi-Kyoung Park, Dong-Yang Lee, Sun-Young Lim, Bu-Il Jung, Ju-Yun Jung, Sung-Ho Cho, Hee-Joo Choi, Min-Yeab Choo, Hyuk Han
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Publication number: 20150199230Abstract: A memory system includes a memory controller, a memory cell array, a location information storage unit, an address mapping table, an address conversion unit, and a mapping information calculation unit. The memory controller generates a logical address signal and an address re-mapping command. The memory cell array includes a plurality of logic blocks. The location information storage unit stores location information corresponding to faulty memory cells included in the memory cell array. The address mapping table stores address mapping information. The address conversion unit converts the logical address signal to a physical address signal corresponding to the memory cell array based on the address mapping information. The mapping information calculation unit generates the address mapping information to reduce the number of logic blocks including the faulty memory cells based on the location information upon the mapping information calculation unit receiving the address re-mapping command.Type: ApplicationFiled: October 27, 2014Publication date: July 16, 2015Inventors: MI-KYOUNG PARK, Dong-Yang Lee, Sun-Young Lim, Bu-Il Jung, Ju-Yun Jung, Sung-Ho Cho, Hee-Joo Choi, Min-Yeab Choo, Hyuk Han
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METHODS OF BOOTING INFORMATION HANDLING SYSTEMS AND INFORMATION HANDLING SYSTEMS PERFORMING THE SAME
Publication number: 20120191964Abstract: A method of booting an information handling system including a volatile memory device to be selectively tested during a booting operation, the method comprising a step of reading current system configuration information from the information handling system, a step of comparing the current system configuration information with corresponding prestored system configuration information in a nonvolatile memory device, and a step of selectively performing a test for the volatile memory device according to a result of the comparison.Type: ApplicationFiled: December 8, 2011Publication date: July 26, 2012Inventors: JONG-MIN LEE, Hyung-Chan Choi, Hee-Joo Choi, Seung-Man Shin -
Patent number: 7979760Abstract: Provided is a test system conducting a parallel bit test. The test system, conducting a parallel bit test on a plurality of memory modules mounted on a socket, comprises a plurality of counters and a comparator. Each of the counters counts the number of data output signals in the same logic state, among the data output signals outputted from each memory of the memory modules, and outputs a count signal. The comparator compares the count signal outputted from each of the counters and outputs a comparison signal corresponding to a defect of the memory modules. According to the test system, defects in a memory module can be accurately detected and a possibility of an error in the detection can be reduced when a plurality of memory modules are tested, as compared to conventional test systems.Type: GrantFiled: March 6, 2009Date of Patent: July 12, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Byoung-sul Kim, Seung-hee Lee, Jung-kuk Lee, Hee-joo Choi
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Publication number: 20110001467Abstract: A method of optimizing a driving voltage of an electronic device includes; iteratively varying the level of a driving voltage provided to the electronic device and performing an operation of the electronic device with each iteration until the operation fails, and then selecting as an operating level for the driving voltage, a level of the driving voltage for an iteration just prior to an iteration in which the operation fails.Type: ApplicationFiled: June 1, 2010Publication date: January 6, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung Chan CHOI, Hee Joo CHOI, Seung Man SHIN, Hui-Chung BYUN
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Publication number: 20090228747Abstract: Provided is a test system conducting a parallel bit test. The test system, conducting a parallel bit test on a plurality of memory modules mounted on a socket, comprises a plurality of counters and a comparator. Each of the counters counts the number of data output signals in the same logic state, among the data output signals outputted from each memory of the memory modules, and outputs a count signal. The comparator compares the count signal outputted from each of the counters and outputs a comparison signal corresponding to a defect of the memory modules. According to the test system, defects in a memory module can be accurately detected and a possibility of an error in the detection can be reduced when a plurality of memory modules are tested, as compared to conventional test systems.Type: ApplicationFiled: March 6, 2009Publication date: September 10, 2009Inventors: Byoung-sul Kim, Seung-hee Lee, Jung-kuk Lee, Hee-joo Choi
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Patent number: 7583509Abstract: A memory module and a memory system are provided. The memory module includes a first circuit board on which at least one memory chip is mounted, a second circuit board on which at least one memory chip is mounted, and a flexible coupler electrically connecting the first circuit board to the second circuit board. The memory module is bendable and is configured to extend around a memory controller. The memory chips are electrically coupled with the memory controller via a respective plurality of signal lines. The bendable memory module is configured to be bent around the memory controller such that respective lengths of the signal lines are equal.Type: GrantFiled: January 4, 2006Date of Patent: September 1, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: In-su Choi, Joon-hee Lee, Hee-joo Choi, Il-guy Jung
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Patent number: 7441167Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.Type: GrantFiled: June 11, 2007Date of Patent: October 21, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-Cheul Kim, Hee-Joo Choi, Kae-Won Ha, Joon-Hee Lee
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Patent number: 7421558Abstract: A memory system for controlling interface timing in a memory module and a related timing control method are disclosed. The memory system comprises a memory module having a memory module controller configured to control interface timing of a plurality of memory devices in accordance with memory information and memory signal information. The memory information includes memory initialization information and interface timing information for the plurality of memory devices.Type: GrantFiled: October 24, 2005Date of Patent: September 2, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-joo Choi, Joon-hee Lee, Dong-jun Kim
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Publication number: 20080005631Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.Type: ApplicationFiled: June 11, 2007Publication date: January 3, 2008Inventors: Youn-Cheul Kim, Hee-Joo Choi, Kae-Won Ha, Joon-Hee Lee
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Patent number: 7289380Abstract: A voltage level shifter for a semiconductor memory device includes a VPP level control circuit that is configured to detect a VPP voltage and to change the VPP voltage in response to a package burn-in mode signal and a test mode signal independent of at least one direct current voltage generated in response to the package burn-in mode signal.Type: GrantFiled: October 4, 2005Date of Patent: October 30, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-jun Kim, Hee-joo Choi, Kae-won Ha
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Patent number: 7246280Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.Type: GrantFiled: March 22, 2005Date of Patent: July 17, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-Cheul Kim, Hee-Joo Choi, Kae-Won Ha, Joon-Hee Lee
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Publication number: 20060176723Abstract: A memory module and a memory system are provided. The memory module includes a first circuit board on which at least one memory chip is mounted, a second circuit board on which at least one memory chip is mounted, and a flexible coupler electrically connecting the first circuit board to the second circuit board. The memory module is bendable and is configured to extend around a memory controller. The memory chips are electrically coupled with the memory controller via a respective plurality of signal lines. The bendable memory module is configured to be bent around the memory controller such that respective lengths of the signal lines are equal.Type: ApplicationFiled: January 4, 2006Publication date: August 10, 2006Inventors: In-su Choi, Joon-hee Lee, Hee-joo Choi, Il-guy Jung
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Publication number: 20060104134Abstract: A voltage level shifter for a semiconductor memory device includes a VPP level control circuit that is configured to detect a VPP voltage and to change the VPP voltage in response to a package burn-in mode signal and a test mode signal independent of at least one direct current voltage generated in response to the package burn-in mode signal.Type: ApplicationFiled: October 4, 2005Publication date: May 18, 2006Inventors: Dong-jun Kim, Hee-joo Choi, Kae-won Ha
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Publication number: 20060090054Abstract: A memory system for controlling interface timing in a memory module and a related timing control method are disclosed. The memory system comprises a memory module having a memory module controller configured to control interface timing of a plurality of memory devices in accordance with memory information and memory signal information. The memory information includes memory initialization information and interface timing information for the plurality of memory devices.Type: ApplicationFiled: October 24, 2005Publication date: April 27, 2006Inventors: Hee-joo Choi, Joon-hee Lee, Dong-jun Kim