Abstract: A memory device comprising: a memory cell array, and a controller configured to connect, in a first interval equal to or longer than a bit line setup interval, each of first and second bit lines, which are connected to cells respectively having first and second program states, to a node of a first permission voltage, connect, in the first interval, a third bit line, which is connected to a cell having a program prohibition state, to a node of a prohibition voltage, maintain, in a second interval that is equal to or shorter than a program pulse application interval, the respective connections of the first bit line and the third bit line, and disconnect, in the second interval, the second bit line from the node of the first permission voltage to apply the second bit line with a second permission voltage.

Abstract: A laser welding apparatus for a secondary battery is provided, with the laser welding apparatus being configured such that a fixing force for a current collector of a secondary battery is improved. The laser welding apparatus reduces the likelihood of human errors and defects in a process of welding the current collector of the secondary battery.

Abstract: A memory device comprising: a memory cell array, and a controller configured to connect, in a first interval equal to or longer than a bit line setup interval, each of first and second bit lines, which are connected to cells respectively having first and second program states, to a node of a first permission voltage, connect, in the first interval, a third bit line, which is connected to a cell having a program prohibition state, to a node of a prohibition voltage, maintain, in a second interval that is equal to or shorter than a program pulse application interval, the respective connections of the first bit line and the third bit line, and disconnect, in the second interval, the second bit line from the node of the first permission voltage to apply the second bit line with a second permission voltage.

Abstract: A memory device and a method of operating the same are provided. The memory device may include a peripheral circuit configured to perform a plurality of program loops and program a page selected from among the plurality of pages, wherein the peripheral circuit may count a number of memory cells whose threshold voltages have increased up to a first target voltage, among a part of memory cells included in the selected page, and may perform a current sensing check operation of determining whether a verify operation performed in a previous program loop has passed or failed, and a control logic circuit configured to control the peripheral circuit so that the current sensing check operation is performed when the number of memory cells whose threshold voltages have increased up to the first target voltage, is equal to or greater than a reference number of memory cells.

Abstract: A semiconductor memory device, and a method of operation, include: a memory block coupled with a plurality of word lines and a plurality of bit lines; a peripheral circuit configured to perform a program operation and a read operation on the memory block; and control logic configured to control the peripheral circuit such that a word line overdrive period overlaps with a bit line overdrive period in a bit line precharge operation during at least one of the program operation and the read operation.

Abstract: A memory device and a method of operating the same are provided. The memory device may include a peripheral circuit configured to perform a plurality of program loops and program a page selected from among the plurality of pages, wherein the peripheral circuit may count a number of memory cells whose threshold voltages have increased up to a first target voltage, among a part of memory cells included in the selected page, and may perform a current sensing check operation of determining whether a verify operation performed in a previous program loop has passed or failed, and a control logic circuit configured to control the peripheral circuit so that the current sensing check operation is performed when the number of memory cells whose threshold voltages have increased up to the first target voltage, is equal to or greater than a reference number of memory cells.

Abstract: A memory device includes drain select lines, source select lines, a plurality of word lines arranged between the drain select lines and the source select lines, and a peripheral circuit configured to perform a program operation on selected memory cells connected to a selected word line among the plurality of word lines. The peripheral circuit includes a voltage generator configured to generate a voltage for initializing a channel of a plurality of memory cells respectively connected to the plurality of word lines in a program phase among a plurality of phases included in the program operation.

Abstract: An electronic device includes drain select lines, source select lines, a plurality of word lines arranged between the drain select lines and the source select lines, and a peripheral circuit configured to perform a program operation on selected memory cells connected to a selected word line among the plurality of word lines. The peripheral circuit includes a voltage generator configured to generate a voltage for initializing a channel of a plurality of memory cells respectively connected to the plurality of word lines in a program phase among a plurality of phases included in the program operation.

Abstract: A semiconductor memory device, and a method of operation, include: a memory block coupled with a plurality of word lines and a plurality of bit lines; a peripheral circuit configured to perform a program operation and a read operation on the memory block; and control logic configured to control the peripheral circuit such that a word line overdrive period overlaps with a bit line overdrive period in a bit line precharge operation during at least one of the program operation and the read operation.