Abstract: A display device according to an embodiment includes: a substrate; a transistor that is disposed on the substrate; a light emitting diode that is disposed on the substrate, and connected to the transistor; and a passivation layer that is disposed between the transistor and the light emitting diode, wherein a surface step of the passivation layer is within a range of and including 1 nm to 30 nm.

Abstract: Disclosed is a secondary battery pouch film, including an outer layer, a metal layer, and a sealant layer, wherein the sealant layer includes a cast polypropylene (CPP) layer and an extruded polypropylene (PP) layer, and the secondary battery pouch film satisfies the [Equation 1] where A+B<1.354, 0.6?C. In [Equation 1], A is a value obtained by dividing a thickness of the metal layer by a total thickness of the secondary battery pouch film, B is a value obtained by dividing a thickness of the metal layer by a thickness of the sealant layer, and C is a value obtained by dividing a thickness of the extruded polypropylene (PP) layer of the sealant layer by a thickness of the cast polypropylene (CPP) layer of the sealant layer. The pouch film has excellent formability, curling, insulation, bending, and peel strength.

Abstract: A display device includes a first substrate and a second substrate facing each other; and a filling layer disposed between the first substrate and the second substrate. The first substrate comprises a support substrate comprising a display area in which emission areas associated with sub-pixels, are arranged; a light-emitting element layer disposed on one surface of the support substrate; and an encapsulation layer disposed on the light-emitting element layer. The encapsulation layer comprises a first inorganic layer covering the light-emitting element layer; an organic layer disposed on the first inorganic layer and overlapping the light-emitting element layer; and a second inorganic layer disposed on the first inorganic layer and covering the organic layer. A thickness of the first inorganic layer is smaller than a thickness of the second inorganic layer.

Abstract: Disclosed is a positive electrode material for a lithium secondary battery. The positive electrode material includes a positive electrode active material formed of Li—[Mn—Ti]-M-O-based material including a transition metal (M) to enable reversible intercalation and deintercalation of lithium and molybdenum oxide. The positive electrode active material is coated with the molybdenum oxide to form a coating layer on a surface thereof.

Abstract: An electroluminescent display device includes an electroluminescent display device includes a substrate; a first pixel row on the substrate including a first plurality of pixels arranged along a first direction; a second pixel row on the substrate including a second plurality of pixels arranged along the first direction, the second pixel row being spaced apart from the first pixel row in a second direction; a first groove between the first and second pixel rows; and a light emitting diode in each pixel of the first and second pixel rows, wherein the first groove includes a first portion at one end of the first pixel row, a second portion at the other end of the first pixel row and a third portion between the first and second portions, and wherein third portion is smaller than the first portion and greater than the second portion.

Abstract: Provided is a fluorine-doped tin oxide support, a platinum catalyst for a fuel cell having the same, and a method for producing the same. Also described is a high electrical conductivity and electrochemical durability by doping fluorine to the tin oxide-based support through an electrospinning process. Thus, while resolving a degradation issue of the carbon support in the conventional commercially available platinum/carbon (Pt/C) catalyst, what is designed is to minimize an electrochemical elution of dopant or tin, which is a limitation of the tin oxide support itself and has excellent performance as a catalyst for a fuel cell.

Abstract: Provided is a peptide composition for preventing or treating Alzheimer's dementia. A peptide or a salt substituent thereof according to the presently claimed subject matter exhibits effects such as suppression of LPS-mediated cytokine production, suppression of LPS-induced neuroinflammation, amelioration of cognitive impairment, suppression of beta amyloid or tau protein aggregation, and suppression of neuronal loss. The polypeptide or the salt substituent thereof can permeate the blood-brain barrier, and thus, is expected to be usefully used for preventing or treating Alzheimer's dementia.

Abstract: Disclosed are a method for manufacturing a secondary battery pouch film having at least an outer layer, a metal layer, a primer layer, and a sealant layer, or at least an outer layer, a metal layer, a primer layer, a melt-extrusion resin layer, and a sealant layer in this order, the method including: a drying process of applying and heating a primer layer composition on the metal layer so as to dry the primer layer composition and cure at least a part of the primer layer composition. The organic solvent-based emulsion composition contains acid-modified polypropylene and a curing agent and has a curing start temperature of 150° C. or lower, preferably 135° C. to 150° C., and a drying process temperature of 150° C. or lower, preferably 135° C. to 150° C. The method is not subjected to a thermal lamination process when laminating sealant layer.

Abstract: Disclosed are a method for manufacturing a secondary battery pouch film having at least an outer layer, a metal layer, a primer layer, and a sealant layer, or at least an outer layer, a metal layer, a primer layer, a melt-extrusion resin layer, and a sealant layer in this order, the method including: a drying process of applying and heating a primer layer composition on the metal layer so as to dry the primer layer composition and cure at least a part of the primer layer composition. The organic solvent-based emulsion composition contains acid-modified polypropylene and a curing agent and has a curing start temperature of 150° C. or lower, preferably 135° C. to 150° C., and a drying process temperature of 150° C. or lower, preferably 135° C. to 150° C. The method is not subjected to a thermal lamination process when laminating sealant layer.

Abstract: A method of interpolating a signal output from an image sensor including a pixel array having an M×N matrix as a basic pixel block where M and N are integers is provided. The method includes selecting a target pixel signal from among pixel signals output from the basic pixel block; and converting a pattern of a pixel signal output from the pixel array into a Bayer pattern by converting a pixel signal output from the basic pixel block into the Bayer pattern through an operation on the target pixel signal and a neighboring pixel signal of the target pixel signal and interpolating an output signal converted into the Bayer pattern.

Abstract: A method of interpolating a signal output from an image sensor including a pixel array having an M×N matrix as a basic pixel block where M and N are integers is provided. The method includes selecting a target pixel signal from among pixel signals output from the basic pixel block; and converting a pattern of a pixel signal output from the pixel array into a Bayer pattern by converting a pixel signal output from the basic pixel block into the Bayer pattern through an operation on the target pixel signal and a neighboring pixel signal of the target pixel signal and interpolating an output signal converted into the Bayer pattern.

Abstract: A semiconductor integrated circuit including a plurality of cores and/or a plurality of user defined logic (UDL) circuits, also includes a scan signal converting circuit to generate a plurality of scan signals to test the cores and/or the circuits adopting various scan styles in core-based design. The scan signal converting circuit converts scan signals corresponding one of the scan styles into various scan signals to control shift and normal operation of the embedded plural cores and/or the UDL circuits. As a result, the integrated circuit having a plurality of cores and/or the UDL circuits can be tested by the generated various scan signals from the scan signal converting circuit, under control of the scan signals corresponding to one of the scan styles. Therefore, the integrated circuit can easily perform test algorithms such as automatic test-pattern generation (ATPG) algorithm, and the like.

Abstract: A semiconductor integrated circuit including a plurality of cores and/or a plurality of user defined logic (UDL) circuits, also includes a scan signal converting circuit to generate a plurality of scan signals to test the cores and/or the circuits adopting various scan styles in core-based design. The scan signal converting circuit converts scan signals corresponding one of the scan styles into various scan signals to control shift and normal operation of the embedded plural cores and/or the UDL circuits. As a result, the integrated circuit having a plurality of cores and/or the UDL circuits can be tested by the generated various scan signals from the scan signal converting circuit, under control of the scan signals corresponding to one of the scan styles. Therefore, the integrated circuit can easily perform test algorithms such as automatic test-pattern generation (ATPG) algorithm, and the like.