Abstract: A fingerprint sensor package includes a first substrate having a core insulating layer with a first surface and a second surface, and a through-hole passing through the first surface and the second surface, a first bonding pad disposed on the second surface of the core insulating layer, and an external connection pad, a second substrate disposed in the through-hole of the core insulating layer and including a plurality of first sensing patterns, a plurality of second sensing patterns, and a second bonding pad, a conductive wire connecting the first bonding pad and the second bonding pad to each other, a controller chip disposed on the second substrate, and a molding layer disposed on the second surface of the core insulating layer, filling the through-hole, covering the second substrate and the first bonding pad, and spaced apart from the external connection pad.

Abstract: A fingerprint sensor package includes a first substrate having a core insulating layer with a first surface and a second surface, and a through-hole passing through the first surface and the second surface, a first bonding pad disposed on the second surface of the core insulating layer, and an external connection pad, a second substrate disposed in the through-hole of the core insulating layer and including a plurality of first sensing patterns, a plurality of second sensing patterns, and a second bonding pad, a conductive wire connecting the first bonding pad and the second bonding pad to each other, a controller chip disposed on the second substrate, and a molding layer disposed on the second surface of the core insulating layer, filling the through-hole, covering the second substrate and the first bonding pad, and spaced apart from the external connection pad.

Abstract: A semiconductor package includes a package substrate with first and second mounting regions at a top surface of the package substrate, a first semiconductor chip disposed on the first mounting region, a second semiconductor chip disposed on the second mounting region, an interposer substrate disposed on the second mounting region and covering the second semiconductor chip, a plurality of conductive connectors extending from a bottom surface of the interposer substrate to the top surface of the package substrate and laterally spaced apart from the second semiconductor chip, and a third semiconductor chip on a top surface of the interposer substrate. A first distance between a top surface of the first semiconductor chip and the top surface of the package substrate is greater than a second distance between the top surface of the interposer substrate and the top surface of the package substrate.

Abstract: A storage device includes at least one non-volatile memory device, a first temperature sensor and a second temperature sensor arranged adjacent to the at least one non-volatile memory device, and a controller controlling an operation performance level of the at least one non-volatile memory device based on a plurality of performance tables, a first temperature detected by the first temperature sensor, and a second temperature detected by the second temperature sensor. Each performance table includes a plurality of entries, and each entry includes information regarding the operation performance level of the at least one non-volatile memory device. Each performance table corresponds to a result of a calculation regarding the first temperature and the second temperature.

Abstract: A storage device includes at least one non-volatile memory device, a first temperature sensor and a second temperature sensor arranged adjacent to the at least one non-volatile memory device, and a controller controlling an operation performance level of the at least one non-volatile memory device based on a plurality of performance tables, a first temperature detected by the first temperature sensor, and a second temperature detected by the second temperature sensor. Each performance table includes a plurality of entries, and each entry includes information regarding the operation performance level of the at least one non-volatile memory device. Each performance table corresponds to a result of a calculation regarding the first temperature and the second temperature.

Abstract: Disclosed is a storage device, which includes a first nonvolatile memory device that stores user data, a second nonvolatile memory device that stores status information for fault analysis, a voltage detect circuit that detects whether an input voltage received at the storage device through a connector exceeds a reference voltage and outputs an over-voltage detect signal when the input voltage exceeds the reference voltage, a status display device that displays a status of the input voltage in response to a blink enable signal, and a storage controller that stores or reads the user data in or from the first nonvolatile memory device, outputs the blink enable signal to the status display device in response to the over-voltage detect signal, and stores the status information in the second nonvolatile memory device.

Abstract: A semiconductor package includes a semiconductor chip and a polydimethylsiloxane (PDMS) layer that is provided on the semiconductor chip and of which upper surface is exposed to the outside. Since the semiconductor package may include the PDMS layer, heat emitting performance of the semiconductor package in a vacuum state may improve.

Abstract: A semiconductor package includes a semiconductor chip and a polydimethylsiloxane (PDMS) layer that is provided on the semiconductor chip and of which upper surface is exposed to the outside. Since the semiconductor package may include the PDMS layer, heat emitting performance of the semiconductor package in a vacuum state may improve.

Abstract: A semiconductor module includes a substrate, a first package mounted on the substrate, second packages mounted on the substrate, a label layer provided on the substrate, and a heat transfer structure interposed between the substrate and the label layer and overlapping at least two of the second packages in a plan view of the module.

Abstract: An operating method of a memory controller to control a nonvolatile memory device includes receiving information about operation failure from the nonvolatile memory device, receiving lock-out status information from the nonvolatile memory device, determining whether a lock-out signal is output based on the lock-out status information, and determining a failure block corresponding to the information about the operation failure as a normal block or a bad block depending on the determination result.

Abstract: A semiconductor module includes a substrate, a first package mounted on the substrate, second packages mounted on the substrate, a label layer provided on the substrate, and a heat transfer structure interposed between the substrate and the label layer and overlapping at least two of the second packages in a plan view of the module.

Abstract: A semiconductor module includes a substrate, a first package mounted on the substrate, second packages mounted on the substrate, a label layer provided on the substrate, and a heat transfer structure interposed between the substrate and the label layer and overlapping at least two of the second packages in a plan view of the module.

Abstract: A semiconductor module includes a substrate, a first package mounted on the substrate, second packages mounted on the substrate, a label layer provided on the substrate, and a heat transfer structure interposed between the substrate and the label layer and overlapping at least two of the second packages in a plan view of the module.

Abstract: A power supply management circuit manages transfer of power that is supplied to a peripheral device from a power supply device. The power supply management circuit includes a current limiter and one or more capacitors. The current limiter limits intensity of first current received from the power supply device through an input terminal to be smaller than or equal to limitation intensity, and outputs second current having intensity limited to be smaller than or equal to the limitation intensity through an output terminal connected to the peripheral device. When the intensity of the first current exceeds the limitation intensity, the capacitors output third current through the output terminal.

Abstract: An operating method of a memory controller to control a nonvolatile memory device includes receiving information about operation failure from the nonvolatile memory device, receiving lock-out status information from the nonvolatile memory device, determining whether a lock-out signal is output based on the lock-out status information, and determining a failure block corresponding to the information about the operation failure as a normal block or a bad block depending on the determination result.

Abstract: Disclosed is a printed circuit hoard. The printed circuit board includes a plurality of insulation layers and a plurality of pattern layers alternately stacked. The printed circuit board includes a plurality of device areas on which semiconductor packages are mounted and a peripheral area adjacent the device areas. An electrostatic discharge pattern is in a respective pattern layer among the plurality of pattern layers and is disposed at a boundary region between a respective device area of the plurality of device areas and the peripheral area.

Abstract: A storage device may include a nonvolatile memory including a plurality of memory blocks and a memory controller configured to determine a comparison between an idle current value of the nonvolatile memory and a reference current value and to adjust, based on the comparison, a start temperature at which the storage device begins operating speed control of the storage device.

Abstract: A semiconductor module includes a substrate, a first package mounted on the substrate, second packages mounted on the substrate, a label layer provided on the substrate, and a heat transfer structure interposed between the substrate and the label layer and overlapping at least two of the second packages in a plan view of the module.

Abstract: A storage device includes memories and a controller. The controller controls first and second program operations on the memory. When a temperature of the memory is lower than a reference value, the controller controls execution of the first program operation. When the temperature of the memory is equal to or higher than the reference value, the controller controls execution of the second program operation which consumes a smaller amount of power than the first program operation. The controller adjusts an operational condition of the memory such that bandwidth on the memory remains equivalent during the first and second program operations.

Abstract: A storage device includes memories and a controller. The controller controls first and second program operations on the memory. When a temperature of the memory is lower than a reference value, the controller controls execution of the first program operation. When the temperature of the memory is equal to or higher than the reference value, the controller controls execution of the second program operation which consumes a smaller amount of power than the first program operation. The controller adjusts an operational condition of the memory such that bandwidth on the memory remains equivalent during the first and second program operations.