Abstract: A circuit board includes a substrate, a first conductive layer, a first insulating layer and a second conductive layer. The first conductive layer includes a plurality of first conductive portions. The second conductive layer includes a plurality of second conductive portions. A second conductive portion passes through a first via hole in the first insulating layer to be in electrical contact with a first conductive portion. The first conductive layer and the second conductive layer each include at least one main conductive layer, which is capable of creating a first intermetallic compound with solder. At least one of the first conductive layer and the second conductive layer further includes a stop layer capable of creating a second intermetallic compound with the solder. A rate of a reaction between the stop layer and the solder is lower than a rate of a reaction between the main conductive layer and the solder.

Abstract: The present disclosure relates to the field of display technologies, and in particular to a thin film transistor and a method for manufacturing the same, an array substrate and a display device. An active layer of the thin film transistor includes at least two metal oxide semi-conductor layers, the at least two metal oxide semi-conductor layers include a channel layer and a first protection layer, and metals in the channel layer include at least one of indium, gallium and zinc. Praseodymium is doped into the channel layer. And, in the channel layer, a number density of praseodymium atoms in the channel layer gradually decreases with a distance from the first protection layer.

Abstract: A thin film transistor, a shift register unit, a gate driving circuit and a display panel are provided. The M source branches and the N drain branches extend along a first direction and are arranged at intervals; in each of the P source-drain units, the M source branches and the N drain branches are alternately arranged, and M is greater than or equal to N; a semiconductor layer includes sub-channel regions between one drain branch and one source branch adjacent to each other; a sum of widths of the sub-channel regions of the P source-drain units in the first direction is W, and an average length of the sub-channel regions of the P source-drain units in a direction perpendicular to the first direction is L; 12?W/L?400, P, M and N are integers greater than or equal to 1, and P×N?4.

Abstract: This invention relates to the field of genetic molecular breeding, specifically to a pig 10K liquid-phase chip based on multiple single nucleotide-polymorphism and its application. The present invention, while adhering to the basic principles of liquid phase chip design, adds new markers to existing chips and optimizes probes using multiple single nucleotide-polymorphism technology. This results in the generation of more SNP markers with high genotyping quality and moderate linkage disequilibrium with target SNP loci within the probe region, thereby increasing the effective marker count of the chip. The mSNP liquid phase chip of the present invention increases the number of detectable SNPs to 1.5-2 times the number of target SNP markers, addressing the issue of existing chips that only contain target SNPs and cannot provide mSNP markers, without increasing the cost.

Abstract: The present disclosure provides a shift register unit, a gate driving circuit and a display device. The shift register unit provided by the present disclosure includes: an input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, at least one pull-down sub-circuit, at least one first noise reduction sub-circuit, and a reverse bias sub-circuit; the reverse bias sub-circuit is configured to control transistors in at least part of sub-circuits connected to a pull-up node to be in a reverse bias state through a power voltage signal in response to a potential of the pull-up node, or control the transistors in at least part of the sub-circuits connected to the pull-up node to be in the reverse bias state through a cascade signal in response to a potential of a cascade signal terminal.

Abstract: A display substrate, including: a base substrate; and a metal conductive layer, located at a side of the base substrate, and including a core conductive layer and a functional conductive layer laminated along a direction away from the base substrate; a material of the core conductive layer includes a conductive metal material; a material of the functional conductive layer includes a first diffusion barrier metal material and a first adhesion force enhancing metal material, wherein the first diffusion barrier metal material is configured to block diffusion of the conductive metal material, and the first adhesion force enhancing metal material is configured to enhance an adhesion force between the functional conductive layer and a photoresist used in a patterning process of the functional conductive layer; a surface energy of any of first adhesion force enhancing metal materials is less than or equal to 325 mJ/m2.

Abstract: The present application relates to a hydrogel. The hydrogel includes polyvinyl alcohol, sodium carboxymethyl cellulose and Huangshui polysaccharide, and the mass ratio of the mass sum of the polyvinyl alcohol and the sodium carboxymethyl cellulose to the Huangshui polysaccharide is 100:(1.8-8.2). The present application further relates to use of the hydrogel as an adsorbent for a dye. The present application further relates to a method for preparing a hydrogel.

Abstract: An apparatus comprising a first processor comprising first circuitry to track correctable errors detected by a first communication device of a second processor; and second circuitry to communicate with the second processor to initiate, based on the tracked correctable errors, a link recovery procedure for the first communication device.

Abstract: A bottom antireflective coating composition and a method for forming a photoresist relief image. The coating composition comprises a resin containing a structural unit represented by the Formula (1), a structural unit represented by the Formula (2), and a structural unit represented by the Formula (3): The structural unit represented by the Formula (1), the structural unit represented by the Formula (2), and the structural unit represented by the Formula (3) is present in the resin in a molar ratio of (0.1-1000):(0.1-1000):1.

Abstract: The disclosure provides a bifunctional composite membrane, a preparation method and use thereof, and a method for removing a plasticizer in liquor. The bifunctional composite membrane includes a supporting membrane and a dense layer which covers a surface of the supporting membrane, wherein the supporting membrane includes a filtering membrane and an adsorbent, and the adsorbent is dispersed in a pore structure of the filtering membrane.

Abstract: In a data write control method, a write control apparatus currently runs a program in a write-back mode in which data are written to a volatile memory. When the apparatus detects that a quantity of dirty blocks in the volatile memory has reached a threshold, it predicts a first amount of execution progress of the program within a prediction time period under an assumption of the apparatus being in a write-through mode in which data are written to the volatile memory and a non-volatile memory. The apparatus also predicts a second amount of execution progress of the program within the prediction time period under an assumption of the apparatus being in the write-back mode. When the predicted first amount of execution progress exceeds the predicted second amount of execution progress, the apparatus switches from the write-back mode to the write-through mode.

Abstract: In a data write control method, a write control apparatus currently runs a program in a write-back mode in which data are written to a volatile memory. When the apparatus detects that a quantity of dirty blocks in the volatile memory has reached a threshold, it predicts a first amount of execution progress of the program within a prediction time period under an assumption of the apparatus being in a write-through mode in which data are written to the volatile memory and a non-volatile memory. The apparatus also predicts a second amount of execution progress of the program within the prediction time period under an assumption of the apparatus being in the write-back mode. When the predicted first amount of execution progress exceeds the predicted second amount of execution progress, the apparatus switches from the write-back mode to the write-through mode.

Abstract: A data write control method includes detecting a quantity of dirty blocks in a first memory when a write control apparatus is in write-back mode; separately predicting execution progress of a program run by a processor within a danger time period in the two write modes when the quantity of dirty blocks reaches a first preset threshold; when it is predicted that the execution progress of the program run by the processor within the danger time period in write-through mode is faster than the execution progress of the program run by the processor within the danger time period in write-back mode, switching a current data write mode to the write-through mode; and detecting the quantity of dirty blocks when the write control apparatus is in write-through mode and switching the current data write mode to the write-back mode when the quantity of dirty blocks decreases to a second preset threshold.

Abstract: When a data backup apparatus is powered on, a quantity of dead blocks and a quantity of live blocks are counted. After the data backup apparatus is powered off, a proportion occupied by dead blocks corresponding to each sequence access identifier at the power-on time point in a total quantity of sampled cache blocks corresponding to the sequence access identifier, is calculated according to the counted quantities of dead blocks and live blocks that correspond to the sequence access identifier at the time point when the data backup apparatus is powered on. The calculated proportion is compared with a preset threshold, and a dead block in a volatile memory unit is predicted according to a comparison result. During backup, a cache block that is predicted to be a dead block is not backed up.

Abstract: When a data backup apparatus is powered on, a quantity of dead blocks and a quantity of live blocks are counted. After the data backup apparatus is powered off, a proportion occupied by dead blocks corresponding to each sequence access identifier at the power-on time point in a total quantity of sampled cache blocks corresponding to the sequence access identifier, is calculated according to the counted quantities of dead blocks and live blocks that correspond to the sequence access identifier at the time point when the data backup apparatus is powered on. The calculated proportion is compared with a preset threshold, and a dead block in a volatile memory unit is predicted according to a comparison result. During backup, a cache block that is predicted to be a dead block is not backed up.

Abstract: A data write control method includes detecting a quantity of dirty blocks in a first memory when a write control apparatus is in write-back mode; separately predicting execution progress of a program run by a processor within a danger time period in the two write modes when the quantity of dirty blocks reaches a first preset threshold; when it is predicted that the execution progress of the program run by the processor within the danger time period in write-through mode is faster than the execution progress of the program run by the processor within the danger time period in write-back mode, switching a current data write mode to the write-through mode; and detecting the quantity of dirty blocks when the write control apparatus is in write-through mode and switching the current data write mode to the write-back mode when the quantity of dirty blocks decreases to a second preset threshold.