Abstract: A light emitter that operates through a display may cause display artifacts, even when the light emitter operates using non-visible wavelengths. Display artifacts caused by a light emitter that operates through a display may be referred to as emitter artifacts. To mitigate emitter artifacts, operating conditions for a display frame may be used to determine an optimal firing time for the light emitter during that display frame. The operating conditions used to determine the optimal firing time may include emitter operating conditions, display content statistics, display brightness, temperature, and refresh rate. Operating conditions from one or more previous frames may be stored in a frame buffer and may be used to help determine the optimal firing time for the light emitter during a display frame. Pixel values for the display may be modified to mitigate emitter artifacts.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.

Abstract: A light emitter that operates through a display may cause display artifacts, even when the light emitter operates using non-visible wavelengths. Display artifacts caused by a light emitter that operates through a display may be referred to as emitter artifacts. To mitigate emitter artifacts, operating conditions for a display frame may be used to determine an optimal firing time for the light emitter during that display frame. The operating conditions used to determine the optimal firing time may include emitter operating conditions, display content statistics, display brightness, temperature, and refresh rate. Operating conditions from one or more previous frames may be stored in a frame buffer and may be used to help determine the optimal firing time for the light emitter during a display frame. Pixel values for the display may be modified to mitigate emitter artifacts.

Abstract: An electronic device includes an electronic display having an active area comprising a pixel. The electronic device also includes processing circuitry configured to receive image data and predict a change in threshold voltage associated with a transistor of the pixel based at least in part on the image data. Furthermore, the processing circuitry is configured to adjust the image data to generate adjusted image data based at least in part on the predicted change in threshold voltage.

Abstract: A trench is formed in an insulating layer to expose a native fin on a substrate. A replacement fin is deposited on the native fin in the trench. The replacement fin is trimmed laterally.

Abstract: A transistor including a gate stack and source and drain on opposing sides of the gate stack; and a first material and a second material on the substrate, the first material disposed between the substrate and the second material and the channel of the transistor is defined in the second material between the source and drain, wherein the first material and the second material each include an implant and the implant includes a greater solubility in the first material than in the second material. A method for forming an integrated circuit structure including forming a first material on a substrate; forming a second material on the first material; introducing an implant into the second material, wherein the implant includes a greater solubility in the first material than in the second material; annealing the substrate; and forming a transistor on the substrate, the transistor including a channel including the second material.

Abstract: An electronic device includes an electronic display having an active area comprising a pixel. The electronic device also includes processing circuitry configured to receive image data and predict a change in threshold voltage associated with a transistor of the pixel based at least in part on the image data. Furthermore, the processing circuitry is configured to adjust the image data to generate adjusted image data based at least in part on the predicted change in threshold voltage.

Abstract: Techniques are disclosed for forming transistors on the same substrate with varied channel materials. The techniques include forming a replacement material region in the substrate, such region used to form a plurality of fins therefrom, the fins used to form transistor channel regions. In an example case, the substrate may comprise Si and the replacement materials may include Ge, SiGe, and/or at least one III-V material. The replacement material regions can have a width sufficient to ensure a substantially planar interface between the replacement material and the substrate material. Therefore, the fins formed from the replacement material regions can also have a substantially planar interface between the replacement material and the substrate material. One example benefit from being able to form replacement material channel regions with such substantially planar interfaces can include at least a 30 percent improvement in current flow at a fixed voltage.

Abstract: A transistor including a gate stack and source and drain on opposing sides of the gate stack; and a first material and a second material on the substrate, the first material disposed between the substrate and the second material and the channel of the transistor is defined in the second material between the source and drain, wherein the first material and the second material each include an implant and the implant includes a greater solubility in the first material than in the second material. A method for forming an integrated circuit structure including forming a first material on a substrate; forming a second material on the first material; introducing an implant into the second material, wherein the implant includes a greater solubility in the first material than in the second material; annealing the substrate; and forming a transistor on the substrate, the transistor including a channel including the second material.

Abstract: A trench is formed in an insulating layer to expose a native fin on a substrate. A replacement fin is deposited on the native fin in the trench. The replacement fin is trimmed laterally.

Abstract: Techniques are disclosed for forming transistors on the same substrate with varied channel materials. The techniques include forming a replacement material region in the substrate, such region used to form a plurality of fins therefrom, the fins used to form transistor channel regions. In an example case, the substrate may comprise Si and the replacement materials may include Ge, SiGe, and/or at least one III-V material. The replacement material regions can have a width sufficient to ensure a substantially planar interface between the replacement material and the substrate material. Therefore, the fins formed from the replacement material regions can also have a substantially planar interface between the replacement material and the substrate material. One example benefit from being able to form replacement material channel regions with such substantially planar interfaces can include at least a 30 percent improvement in current flow at a fixed voltage.

Abstract: A gated nano-electro-mechanical (NEM) switch employing metal-insulator-metal (MIM) technology and related devices and methods which can facilitate implementation of low-power, radiation-hardened, high-temperature electronic devices and circuits. In one example embodiment a gate electrode is configured as a cantilever beam whose free end is coupled to a MIM stack. The stack moves into bridging contact across a source and drain region when the applied gate voltage generates a sufficient electrostatic force to overcome the mechanical biasing of the cantilever beam. A second set of contacts can be added on the cantilever beam to form a complementary switching structure, or to a separate cantilever beam. The switching can be configured as non-volatile in response to stiction forces. NEM circuits provide a number of advantages within a variety of circuit types, including but not limited to: logic, memory, sleep circuits, pass circuits, and so forth.

Abstract: A scalable nano-electro-mechanical memory cell design that requires only conventional semiconductor fabrication materials and surface micromachining technology, and is suited for use in cross-point memory arrays for very high density non-volatile storage. This design also leverages well established surface-micromachining technology and electro-mechanical device phenomena to achieve an elegantly simple and scalable memory cell structure that can potentially operate with low voltage. An elongate beam is held between a non-deflected state and a deflected state, or between two deflected states, therein defining two binary memory states. Stiction, buried charge layers, or a combination of stiction and buried charge layers can be incorporated to modify the stability of one or both deflected states for the cell. Current through the moveable portion of the elongate beam within the memory cell can be registered utilizing one or more access transistors for reading the data state.

Abstract: A scalable nano-electro-mechanical memory cell design that requires only conventional semiconductor fabrication materials and surface micromachining technology, and is suited for use in cross-point memory arrays for very high density non-volatile storage. This design also leverages well established surface-micromachining technology and electro-mechanical device phenomena to achieve an elegantly simple and scalable memory cell structure that can potentially operate with low voltage. An elongate beam is held between a non-deflected state and a deflected state, or between two deflected states, therein defining two binary memory states. Stiction, buried charge layers, or a combination of stiction and buried charge layers can be incorporated to modify the stability of one or both deflected states for the cell. Current through the moveable portion of the elongate beam within the memory cell can be registered utilizing one or more access transistors for reading the data state.

Abstract: A gated nano-electro-mechanical (NEM) switch employing metal-insulator-metal (MIM) technology and related devices and methods which can facilitate implementation of low-power, radiation-hardened, high-temperature electronic devices and circuits. In one example embodiment a gate electrode is configured as a cantilever beam whose free end is coupled to a MIM stack. The stack moves into bridging contact across a source and drain region when the applied gate voltage generates a sufficient electrostatic force to overcome the mechanical biasing of the cantilever beam. A second set of contacts can be added on the cantilever beam to form a complementary switching structure, or to a separate cantilever beam. The switching can be configured as non-volatile in response to stiction forces. NEM circuits provide a number of advantages within a variety of circuit types, including but not limited to: logic, memory, sleep circuits, pass circuits, and so forth.