Patents by Inventor Hei Ming Shiu
Hei Ming Shiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9418919Abstract: Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board.Type: GrantFiled: January 14, 2011Date of Patent: August 16, 2016Assignee: NXP B.V.Inventors: Roelf Anco Jacob Groenhuis, Markus Björn Erik Noren, Fei-ying Wong, Hei-ming Shiu
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Publication number: 20160211197Abstract: Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board.Type: ApplicationFiled: January 14, 2011Publication date: July 21, 2016Applicant: NXP B.V.Inventors: Roelf Anco Jacob GROENHUIS, Markus Björn Erik NOREN, Fei-ying WONG, Hei-ming SHIU
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Publication number: 20120181678Abstract: Consistent with an example embodiment, there is surface-mountable non-leaded chip carrier for a semiconductor device. The device comprises a first contact. A second contact is relative to the first contact; the second contact has a split therein to provide first and second portions of the second contact arranged relative to one another to lessen tilting of a soldering condition involving attachment of the chip carrier to a printed circuit board.Type: ApplicationFiled: January 14, 2011Publication date: July 19, 2012Applicant: NXP B.V.Inventors: Roelf Anco Jacob GROENHUIS, Markus Björn Erik NOREN, Fei-ying WONG, Hei-ming SHIU
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Patent number: 7494924Abstract: A method for forming reinforced interconnects or bumps on a substrate includes first forming a support structure on the substrate. A substantially filled capsule is then formed around the support structure to form an interconnect. The interconnect can reach a height of up to 300 microns.Type: GrantFiled: March 6, 2006Date of Patent: February 24, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Hei Ming Shiu, On Lok Chau, Gor Amie Lai, Heng Keong Yip, Thoon Khin Chang, Lan Chu Tan
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Patent number: 7422973Abstract: A method for forming multi-layer bumps on a substrate includes depositing an adhesive or a flux on the substrate, depositing a first metal powder on the adhesive, and melting or reflowing the adhesive and first metal powder to form first bumps. An adhesive or a flux and a second metal powder are then deposited on the first bumps, and melted to form second bumps on the first bumps to form multi-layer bumps. The multi-layer bumps are formed without the need for any wet chemicals.Type: GrantFiled: January 27, 2006Date of Patent: September 9, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Hei Ming Shiu, On Lok Chau, Gor Amie Lai
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Patent number: 7279409Abstract: A method for forming multi-layer bumps on a substrate includes depositing a first metal powder on the substrate, and selectively melting or reflowing a portion of the first metal powder to form first bumps. A second metal powder is then deposited on the first bumps, and melted to form second bumps on the first bumps. A masking plate is disposed over the substrate to select the portions of the metal powders that are melted and the metal powders are melted via an irradiation beam. The multi-layer bump is formed without the need for any wet chemicals.Type: GrantFiled: October 31, 2005Date of Patent: October 9, 2007Assignee: Freescale Semiconductor, IncInventors: Hei Ming Shiu, On Lok Chau, Gor Amie Lai
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Patent number: 7262494Abstract: An electronic device (60) including a first integrated circuit (IC) die (62) electrically connected to a first lead frame (64) and a second IC die (66) electrically connected to a second lead frame (68). The first lead frame (64) is electrically connected to the second lead frame (68) by at least one stud bump (72), which is selectively formed where an electrical connection between the first lead frame (64) and the second lead frame (68) is required. The first and second lead frames (64) and (68), the first and second IC dies (62) and (66), and the at least one stud bump (72) are encapsulated by a mold compound (74) to form a 3D package.Type: GrantFiled: March 16, 2005Date of Patent: August 28, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Hei Ming Shiu, On Lok Chau, Fei Ying Wong
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Patent number: 7205178Abstract: A method of packaging an integrated circuit die (12) includes the steps of providing a foil sheet (30) and forming a layer of solder (32) on a first side of the foil sheet. A first side of the integrated circuit die is attached to the solder on the foil sheet. The first side of the die has a layer of metal (34) on it and a second, opposing side of the die includes bonding pads (14). The bonding pads are electrically connected to the solder on the foil sheet with wires (16). The die, the electrical connections, and the first side of the foil sheet are encapsulated with a mold compound (20). The foil sheet is separated from the die and the wires, which forms a packaged integrated circuit (10).Type: GrantFiled: March 24, 2004Date of Patent: April 17, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Hei Ming Shiu, Kam Fai Lee, Ho Wang Wong
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Patent number: 7112871Abstract: A semiconductor device (10) includes a first leadframe (18) having a perimeter (20) that defines a cavity (22) and leads (14) extending inwardly from the perimeter, and a second leadframe (32) having top and bottom surfaces and a die paddle surrounding a die receiving area (36). An integrated circuit (12) is placed within the die receiving area of the second leadframe. The IC has bonding pads (44) located on a peripheral portion of its top surface. The second leadframe and the IC are in facing relation with the first leadframe such that the leads of the first leadframe are electrically connected to respective ones of the bonding pads. A mold compound (50) is injected between the first and second leadframes and covers the second leadframe top surface and a central area of the first surface of the IC. At least the bottom surfaces of the leads are exposed.Type: GrantFiled: January 26, 2005Date of Patent: September 26, 2006Assignee: Freescale Semiconductor, INCInventors: Hei Ming Shiu, Wai Wong Chow, Qing-Chun He
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Patent number: 7056766Abstract: A method of packaging an integrated circuit die (12) includes the steps of forming an array of soft conductive balls (14) in a fixture (30) and flattening opposing sides of the balls. The flattened balls are then transferred from the fixture to a mold masking tape (36). A first side of the IC die is attached to the balls with a die attach adhesive (16) and then wire bonding pads (20) on the die are electrically connected directly to respective balls with wires (22). An encapsulant (24) is formed over the die, the electrical connections, and a top portion of the formed balls. The tape is removed and adjacent, encapsulated dice are separated via saw singulation. The result is an encapsulated IC having a bottom side with exposed balls.Type: GrantFiled: December 9, 2003Date of Patent: June 6, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Hei Ming Shiu, Wai Wong Chow, Nan Xu
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Patent number: 6905910Abstract: An image sensor device includes a first, QFN type leadframe to which a sensor IC is electrically connected. A second leadframe is provided for holding a lens. A third leadframe is positioned between the first and second leadframes to appropriately space the IC from the lens. Multiple sensor devices are assembled at the same time by the use of leadframe panels.Type: GrantFiled: January 6, 2004Date of Patent: June 14, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Hei Ming Shiu, Wai Wong Chow, Kam Fai Lee
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Patent number: 6867072Abstract: A semiconductor device (10) includes a first leadframe (18) having a perimeter (20) that defines a cavity (22) and leads (14) extending inwardly from the perimeter, and a second leadframe (32) having top and bottom surfaces and a die paddle surrounding a die receiving area (36). An integrated circuit (12) is placed within the die receiving area of the second leadframe. The IC has bonding pads (44) located on a peripheral portion of its top surface. The second leadframe and the IC are in facing relation with the first leadframe such that the leads of the first leadframe are electrically connected to respective ones of the bonding pads. A mold compound (50) is injected between the first and second leadframes and covers the second leadframe top surface and a central area of the first surface of the IC. At least the bottom surfaces of the leads are exposed.Type: GrantFiled: January 7, 2004Date of Patent: March 15, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Hei Ming Shiu, Wai Wong Chow, Qing-Chun He