Abstract: A component (10) includes a substrate (15), a cap wafer (23), and a protection layer (28) formed over a surface of the cap wafer (23). Together, the protection layer (28) and the cap wafer (23) form a cap structure (39) that is bonded to the substrate (15) via a bonding layer (33). An opening (47) is formed in the cap wafer (23) by etching the cap wafer (23). The protection layer (28) provides protection during etching of the cap wafer (23) for the underlying bonding layer (33) and devices (11,12) formed in the substrate (15).

Abstract: A component (10) includes a substrate (15), a cap wafer (23), and a protection layer (28) formed over a surface of the cap wafer (23). Together, the protection layer (28) and the cap wafer (23) form a cap structure (39) that is bonded to the substrate (15) via a bonding layer (33). An opening (47) is formed in the cap wafer (23) by etching the cap wafer (23). The protection layer (28) provides protection during etching of the cap wafer (23) for the underlying bonding layer (33) and devices (11,12) formed in the substrate (15).

Abstract: Portions of a semiconductor device (10,30) are formed from a dielectric layer (16,38,46) which is deposited using a plasma enhanced chemical vapor deposition (PECVD) process which adds trimethylphosphite as a dopant source during the deposition. A first embodiment forms sidewall spacers (17) adjacent to a gate structure (14) and forms doped regions (19) under the sidewall spacers (17) by annealing the dielectric layer (16) and driving phosphorus into a substrate (11). A second embodiment uses the trimethylphosphite doped film as an interlevel dielectric layer (38) which can be planarized to provide a flat surface for the formation of metal interconnect lines. A third embodiment of the present invention uses the trimethylphosphite doped film as a passivation layer (46) which is deposited in a single step process and has a phosphorus concentration to getter mobile ions.