Abstract: A static direct-access memory block for a receiving sensor, including a memory cell array, a row address decoder, a column data multiplexer, a read and write module having a read amplifier and a write driver, a control logic circuit, a data input, and a data output. The static direct-access memory block has internal memory clocking. At least one adder for adding input data coming in through the data input is integrated in the static direct-access memory block. The at least one adder is situated between the data input and the read and write module. This allows the read and write operations to be optimized and, thus, the power consumption to be decreased. A receiving sensor for a radar or lidar system, including an application-specific integrated circuit. The application-specific integrated circuit includes at least one static direct-access memory block.

Abstract: A static direct-access memory block for a receiving sensor, including a memory cell array, a row address decoder, a column data multiplexer, a read and write module having a read amplifier and a write driver, a control logic circuit, a data input, and a data output. The static direct-access memory block has internal memory clocking. At least one adder for adding input data coming in through the data input is integrated in the static direct-access memory block. The at least one adder is situated between the data input and the read and write module. This allows the read and write operations to be optimized and, thus, the power consumption to be decreased. A receiving sensor for a radar or lidar system, including an application-specific integrated circuit. The application-specific integrated circuit includes at least one static direct-access memory block.

Abstract: In one aspect a method of storing data in an integrated circuit may include identifying a group of storage sites from a plurality of storage sites; selecting a plurality of storage levels, each storage level being assignable to a storage site in the group of storage sites; and assigning a unique storage level to each of the storage sites in the group of storage sites, each unique storage level assigned from the plurality of storage levels.

Abstract: An integrated semiconductor memory device includes a first input amplifier which, compared with a second input amplifier, has a lower sensitivity with regard to level fluctuations of its respective input signal. A control circuit drives a controllable switch in such a way that when a noisy clock signal is applied to the integrated semiconductor memory device, the less sensitive input amplifier is used for generating an internal clock signal. If, by contrast, a lower-noise clock signal is applied to the integrated semiconductor memory device, the control circuit drives the controllable switch in such a way that the more sensitive input amplifier is used for generating the internal clock signal. The changeover of the controllable switch is effected after evaluation of a bit sequence applied to a further input terminal of the integrated semiconductor memory device.

Abstract: An integrated semiconductor memory device includes a first input amplifier which, compared with a second input amplifier, has a lower sensitivity with regard to level fluctuations of its respective input signal. A control circuit drives a controllable switch in such a way that when a noisy clock signal is applied to the integrated semiconductor memory device, the less sensitive input amplifier is used for generating an internal clock signal. If, by contrast, a lower-noise clock signal is applied to the integrated semiconductor memory device, the control circuit drives the controllable switch in such a way that the more sensitive input amplifier is used for generating the internal clock signal. The changeover of the controllable switch is effected after evaluation of a bit sequence applied to a further input terminal of the integrated semiconductor memory device.

Abstract: In a memory element with a first number of memory cells having a first retention time for holding a content of the memory cells and a second number of memory cells having a second retention time for holding the content of the memory cell, a method for refreshing the memory cells comprises a step of refreshing the first number of memory cells when reaching the first retention time and a step of refreshing the second number of memory cells when reaching the second retention time. An apparatus for refreshing the memory cells of the memory element is provided for refreshing the first number of memory cells when reaching the first retention time, and for refreshing the second number of memory cells when reaching the second retention time.

Abstract: An integrated circuit has a synchronous circuit and an asynchronous circuit. A clock-controlled input register circuit and an output register circuit for storing data are each connected to the synchronous circuit and the asynchronous circuit. Data are transferred from the synchronous circuit into the input register circuit, from where they are transferred into the asynchronous circuit and processed in the asynchronous circuit. Processed data are transferred into the output register circuit. A sequence controller generates a respective control clock signal for the register circuits in a manner dependent on the data processing duration of the asynchronous circuit. This enables a high data throughput between the synchronous circuit and the asynchronous circuit independently of a clock frequency of the synchronous circuit.

Abstract: An electronic circuit for generating an output voltage has a defined temperature dependence, a bandgap circuit for generating a defined temperature-constant voltage and a temperature-dependent current with a defined temperature dependence, and a conversion circuit for generating the output voltage from the temperature-dependent current and the temperature-constant voltage. The conversion circuit has a first resistor at whose first terminal the temperature-constant voltage is applied, and whose second terminal is connected to a first terminal of a second resistor. The second terminal of the second resistor is connected to a supply voltage potential, and a first terminal of a third resistor is connected to the second terminal of the first resistor. The temperature-dependent current is supplied to a second terminal of the third resistor, and it being possible to tap the output voltage at the second terminal of the third resistor.

Abstract: A circuit configuration contains a flow controller that can be put into a plurality of states and outputs a respective command, in a respective one of the states, to a circuit component to be controlled. The flow controller has at least one asynchronously operating delay circuit via which the flow controller moves from one of the states into the respective next state. The delay circuit has a further signal path connected in parallel with it which contains a clock-controlled multivibrator. The delay circuit and the further signal path are able to be operated alternatively using a switching device. The circuit allows, particularly in integrated memories, an asynchronous access command sequence, in a first mode, and a synchronous access command sequence, in a second mode, to be produced for the flow controller, particularly in communication with a test unit.

Abstract: A circuit configuration contains a flow controller that can be put into a plurality of states and that outputs a respective command, in a respective one of the states, to a circuit component to be controlled. The flow controller has at least one asynchronously operating delay circuit via which the flow controller moves from one of the states into the respective next state. The delay circuit has a further signal path connected in parallel with it which contains a clock-controlled multivibrator. The delay circuit and the further signal path are able to be operated alternatively using a switching device. The circuit allows, particularly in integrated memories, an asynchronous access command sequence, in a first mode, and a synchronous access command sequence, in a second mode, to be produced for the flow controller, particularly in communication with a test unit.

Abstract: In a memory element with a first number of memory cells having a first retention time for holding a content of the memory cells and a second number of memory cells having a second retention time for holding the content of the memory cell, a method for refreshing the memory cells comprises a step of refreshing the first number of memory cells when reaching the first retention time and a step of refreshing the second number of memory cells when reaching the second retention time. An apparatus for refreshing the memory cells of the memory element is provided for refreshing the first number of memory cells when reaching the first retention time, and for refreshing the second number of memory cells when reaching the second retention time.

Abstract: An electronic circuit for generating an output voltage has a defined temperature dependence, a bandgap circuit for generating a defined temperature-constant voltage and a temperature-dependent current with a defined temperature dependence, and a conversion circuit for generating the output voltage from the temperature-dependent current and the temperature-constant voltage. The conversion circuit has a first resistor at whose first terminal the temperature-constant voltage is applied, and whose second terminal is connected to a first terminal of a second resistor. The second terminal of the second resistor is connected to a supply voltage potential, and a first terminal of a third resistor is connected to the second terminal of the first resistor. The temperature-dependent current is impressed at a second terminal of the third resistor, and it being possible to tap the output voltage at the second terminal of the third resistor.

Abstract: In order to shorten an access time and thus to shorten the entire data processing time, a sector size of a memory device is adapted to respective applications. Each application is assigned a respective sector. The access right is checked only once for each application.

Abstract: An integrated circuit has a synchronous circuit and an asynchronous circuit. A clock-controlled input register circuit and an output register circuit for storing data are each connected to the synchronous circuit and the asynchronous circuit. Data are transferred from the synchronous circuit into the input register circuit, from where they are transferred into the asynchronous circuit and processed in the asynchronous circuit. Processed data are transferred into the output register circuit. A sequence controller generates a respective control clock signal for the register circuits in a manner dependent on the data processing duration of the asynchronous circuit. This enables a high data throughput between the synchronous circuit and the asynchronous circuit independently of a clock frequency of the synchronous circuit.

Abstract: An electronic memory device (1) having electrically programmable memory cells, an address bus (30) for addressing the memory cells, and also a controllable programming voltage pump (22) for producing a programming voltage for the memory cells. The electronic memory device is distinguished by a switching device (23) which can be actuated by a test mode signal and which can be used to connect the address bus (30) to the programming voltage pump (22) in a test mode such that a prescribable test programming voltage can be set using supplied address bits.

Abstract: The auto refresh sequence on a DRAM that is divided into memory banks is synchronized with the clock signal acting on the DRAM. A precharge pulse is transmitted during an NOP intermission or is derived from a precharge pulse of another memory bank.

Abstract: An electronic memory device (1) having electrically programmable memory cells, an address bus (30) for addressing the memory cells, and also a controllable programming voltage pump (22) for producing a programming voltage for the memory cells. The electronic memory device is distinguished by a switching device (23) which can be actuated by a test mode signal and which can be used to connect the address bus (30) to the programming voltage pump (22) in a test mode such that a prescribable test programming voltage can be set using supplied address bits.

Abstract: A chip card includes a semiconductor chip that contains at least one memory. In order to supply energy to the chip and to provide for bi-directional data transmission from and to the chip, both contacts and a device for contactless data transmission are provided. A triggerable switch device which is provided on the chip connects the memory either to the contacts or to the device for contactless data transmission as a function of a state of an output signal of a logic circuit connected to at least a voltage supply contact. The switch device assumes a position of repose when it is not triggered and in that position it connects the memory to the device for contactless data transmission, while only upon application of a voltage to the supply voltage contact, triggered by the logic circuit, does it connect the contacts to the memory.

Abstract: A device for processing and storing data, in particular a chip card, includes a first interface with contacts and a second contactless interface for receiving energy or power from and for communication with a terminal device. A first controllable switching device connects either the first or the second interface to a non-volatile semiconductor memory through address, data and control lines. A logic circuit drives the first controllable switching device. A second controllable switching device disposed between the first controllable switching device and the memory can be driven at least by the logic circuit and an address signal present on the address lines.