Abstract: A control device for a gearbox control system of a motor vehicle includes electric components having different high dissipated power, a rigid circuit board which is equipped on both sides with electric components, at least one cooling body on the same side as the circuit board on which the power components are arranged, and a potting compound, which at least partially surrounds the components. The circuit board is secured directly adjacent to the cooling body.

Abstract: A control device for a gearbox control system of a motor vehicle includes electric components having different high dissipated power, a rigid circuit board which is equipped on both sides with electric components, at least one cooling body on the same side as the circuit board on which the power components are arranged, and a potting compound, which at least partially surrounds the components. The circuit board is secured directly adjacent to the cooling body.

Abstract: The present invention relates to a method for a self-boot of an electronic device, wherein an external component is accessible through an interface of the electronic device (101), the method comprising, determining a boot mode for booting the electronic device, wherein the determined boot mode is defined as a secure boot mode; disabling the interface, thereby prohibiting access to the component through the interface, thereby defining a secure state of the electronic device; loading a first code comprising a sequence of executable instructions to be executed for booting the electronic device; loading a second code, the second code being encrypted; and decrypting the second code and executing the second code, thereby enabling the interface, and switching the electronic device from the secure state to a debugging state.

Abstract: A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device included in the one or more slave scan devices, a first request for access to the scan chain to the master scan device. The master scan device and the one or more slave scan devices are connected to the scan chain. The technique also includes receiving, at the requesting slave scan device, an evaluation result from the master scan device and accessing, by the requesting slave scan device, the scan chain in response to the evaluation result indicating access granted. Finally, the technique includes sending, by the requesting slave scan device, one or more second requests for access to the scan chain to the master scan device in response to the evaluation result indicating access denied.

Abstract: A technique for controlling scan access of multiple scan devices (including or more slave scan devices and a master scan device) to a scan chain includes sending, by a requesting slave scan device included in the one or more slave scan devices, a first request for access to the scan chain to the master scan device. The master scan device and the one or more slave scan devices are connected to the scan chain. The technique also includes receiving, at the requesting slave scan device, an evaluation result from the master scan device and accessing, by the requesting slave scan device, the scan chain in response to the evaluation result indicating access granted. Finally, the technique includes sending, by the requesting slave scan device, one or more second requests for access to the scan chain to the master scan device in response to the evaluation result indicating access denied.

Abstract: Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.

Abstract: An integrated circuit (IC) performs self-healing and reconfiguration of a portion of the IC. In response to determining that a portion of the IC should be configured, a clock to the portion of the IC to be configured is halted. That portion of the IC is then configured using a processing core that is included in the IC. The processing core is also used to perform an intended function of the IC that is different than the configuration.

Abstract: An integrated circuit may use a processing core provided for normal operation to diagnose and reconfigure other portions of the integrated circuit by accessing scanrings of storage elements of the other portions of the integrated circuit.

Abstract: Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.

Abstract: Mechanisms, in a processor chip, are provided for obtaining debug data from on-chip logic of the processor chip while the processor chip is in a secure mode of operation. The processor chip is placed into a secure mode of operation in which access to internal logic of the processor chip to control the internal logic of the processor chip, by mechanisms external to the processor chip, is disabled on a debug interface of the processor chip. A triggering condition of the processor chip is detected that is a trigger for initiated debug data collection from the on-chip logic. Debug data collection is performed from the on-chip logic to generate debug data. Data is output, by the processor chip to an external mechanism, on the debug interface based on the debug data.

Abstract: The invention describes an analyzing device for an embedded system (9), which has at least one CPU (1), at least one CPU bus (2), and at least one memory (3). The device includes a communication module (4) for the input or output of analysis data using a test interface (5), which, in addition to control lines, includes at least one group of data lines. The data words and the address words are transmitted alternately or in other succession by way of the test interface. This achieves the advantage of error detection while using few basic cycles of the CPU.

Abstract: A method and apparatus are disclosed for decoding according to a Log-MAP algorithm, a bit sequence encoded by a convolutional encoder and received through a noisy channel. A digital signal processor (DSP) for performing the decoding is provided with an extended core possessing a transition metric calculation unit (153) for calculating transition metric values of the encoder trellis for output to a memory store (101,102) of the DSP, and for output to a unit (154) for performing a Log-MAP add-compare-select operation. The Log-MAP add-compare-select unit (154) calculates updated path metric values of the encoder trellis for storage in a memory store (101,102) of the DSP, and for input to a Log-Likelihood Ratio calculating unit (155). The Log-Likelihood Ratio calculating unit (155) are each controlled by the program control unit (104) of the DSP, and communicate with the data memories (101, 102) of the DSP, via data lines (150, 151, 152).

Abstract: A method and apparatus are disclosed for decoding according to a Log-MAP algorithm, a bit sequence encoded by a convolutional encoder and received through a noisy channel. A digital signal processor (DSP) for performing the decoding is provided with an extended core possessing a transition metric calculation unit (153) for calculating transition metric values of the encoder trellis for output to a memory store (101,102) of the DSP, and for output to a unit (154) for performing a Log-MAP add-compare-select operation. The Log-MAP add-compare-select unit (154) calculates updated path metric values of the encoder trellis for storage in a memory store (101,102) of the DSP, and for input to a Log-Likelihood Ratio calculating unit (155). The Log-Likelihood Ratio calculating unit (155) calculates the Log-Likelihood Ratio of a given data bit to be decoded.