Patents by Inventor Heimanu Niebojewski
Heimanu Niebojewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12376350Abstract: A method for manufacturing a quantum electronic circuit includes etching a semiconducting layer so as to obtain: a plurality of pillars; and a qubit layer; oxidising the flank of each pillar; forming coupling rows and coupling columns; and depositing separation layers leaving a contact surface protrude from each pillar.Type: GrantFiled: September 30, 2022Date of Patent: July 29, 2025Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Heimanu Niebojewski, Thomas Bedecarrats, Benoit Bertrand
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Publication number: 20250159955Abstract: A method for manufacturing an electronic circuit includes forming first electrodes distributed at a constant pitch; forming spacers against the first electrodes; forming a second electrode between two neighbouring spacers; and replacing each spacer with a third electrode. The first, second and third electrodes are thus distributed at an average pitch equal to R/4.Type: ApplicationFiled: November 7, 2024Publication date: May 15, 2025Inventor: Heimanu NIEBOJEWSKI
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Publication number: 20250015212Abstract: A quantum device configured to be able to form an array of quantum dots, the device including for this: an active layer made of a semiconductor material; a plurality of first gates disposed along a plurality of rows; a plurality of second gates disposed along a plurality of columns perpendicular to the rows of the plurality of rows; a plurality of third gates, each third gate of the plurality of third gates being disposed at the intersection of one row of the plurality of rows and one column of the plurality of columns, each third gate being separated from the nearest third gates, on a row by a first gate and on a column by a second gate; a plurality of fourth gates, each fourth gate being disposed between two second gates along the rows and between two first gates along the columns.Type: ApplicationFiled: December 20, 2023Publication date: January 9, 2025Inventors: Benoit BERTRAND, Thomas BEDECARRATS, Heimanu NIEBOJEWSKI
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Publication number: 20250017120Abstract: A quantum device configured to be able to form an array of quantum dots, the device including for this: an active layer made of a semiconductor material; a plurality of first gates disposed along a plurality of rows; a plurality of second gates disposed along a plurality of columns perpendicular to the rows of the plurality of rows; a plurality of third gates, each third gate of the plurality of third gates being disposed at the intersection of one row of the plurality of rows and one column of the plurality of columns, each third gate being separated from the nearest third gates, on a row by a first gate and on a column by a second gate; the active layer including apertures over the entire thickness of the active layer disposed between the rows of the plurality of rows and the columns of the plurality of columns.Type: ApplicationFiled: December 20, 2023Publication date: January 9, 2025Inventors: Benoit BERTRAND, Thomas BEDECARRATS, Heimanu NIEBOJEWSKI
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Publication number: 20240405103Abstract: A method for producing a lateral gate for a semiconductive device, comprising: etching of trenches depositing an electrode laver on the flank of the trenches, and a dielectric material filling. Advantageously, the lateral gate electrostatically controls a distribution of the charge carriers in a metal-oxide-semiconductor (MOS)-type structure, in particular for spin qubit applications.Type: ApplicationFiled: May 30, 2024Publication date: December 5, 2024Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Hamza SAHIN, Benoît BERTRAND, Heimanu NIEBOJEWSKI
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Publication number: 20240321893Abstract: One aspect of the invention relates to an electronic circuit (1) comprising: a semiconductor layer (2), referred to as “qubit layer”; a separation layer (42) extending in contact with the qubit layer (2); first conductive electrodes (61), referred to as “coupling rows”, extending in parallel to the qubit layer (2); second conductive electrodes (62), referred to as “coupling columns”, extending in parallel to the qubit layer (2); third conductive electrodes (71), referred to as “control rows”, extending over the spacer (42); and conductive vias (72), referred to as “control vias”, extending perpendicularly to the face of the qubit layer (2) from the spacer (42) and having one end disposed in proximity to the qubit layer (2).Type: ApplicationFiled: March 21, 2024Publication date: September 26, 2024Inventors: Heimanu NIEBOJEWSKI, Benoit BERTRAND, Thomas BEDECARRATS
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Publication number: 20240222474Abstract: A quantum electronic device comprising: a substrate coated with at least one semiconductor block, insulation zones on either side of the semiconductor block, front gate electrodes on regions of the semiconductor block each forming a quantum dot, one or more exchange electrodes arranged around and at a distance from the semiconductor block, at least one first exchange electrode among the exchange electrodes being provided so as to allow to modulate a tunnel barrier between a first quantum dot and a second quantum dot, this first exchange electrode being formed by a first conductive pad passing through an insulating layer covering the semiconductor block, the insulation zones and the gate electrodes, the first conductive pad having a “lower” end disposed in contact with the first insulation zone.Type: ApplicationFiled: December 13, 2023Publication date: July 4, 2024Inventors: Heimanu NIEBOJEWSKI, Benoit BERTRAND, Etienne NOWAK
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Publication number: 20240213091Abstract: A method is provided for producing a back gate under a semiconductive device surrounded by isolation trenches. The method includes a partial etching of the isolation trenches forming an opening to the sacrificial layer, a selective removal of the sacrificial layer forming a cavity under the device, and a filling of the cavity with a conductive material so as to form the back gate. Advantageously, the formation of the isolation trenches comprises a formation of a sacrificial coating layer at the flanks of the trenches, in contact with the sacrificial layer, before filling with an isolating material, and the partial etching of the trenches comprises a removal of this sacrificial coating layer selectively at the isolating material.Type: ApplicationFiled: December 22, 2023Publication date: June 27, 2024Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Heimanu NIEBOJEWSKI, Thomas BEDECARRATS, Benoit BERTRAND
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Patent number: 12002869Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.Type: GrantFiled: September 2, 2022Date of Patent: June 4, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Lars W. Liebmann, Heimanu Niebojewski, Xuelian Zhu, Lei Sun, Hui Zang
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Publication number: 20230170402Abstract: A method for fabricating a quantum device includes, in order, forming, on a semiconductor active zone resting on a substrate, a stack having at least one layer of gate material and one or more masking layers on the layer of gate material; forming, facing the active zone, a separation trench by etching through the one or more masking layers, the trench having a bottom revealing the at least one layer of gate material; forming, in the one or more masking layers, one or more pairs of masking blocks, each pair including a second masking block facing a first masking block, the first and second masking blocks being disposed on either side of the trench; and forming, in line with each masking block and by etching the at least one layer of gate material, a gate block so as to form one or more pairs of gate blocks.Type: ApplicationFiled: November 28, 2022Publication date: June 1, 2023Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Heimanu NIEBOJEWSKI, Benoît BERTRAND
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Patent number: 11646196Abstract: Making of a transistor structure comprising in this order: forming semiconductor blocks made of SixGe1-x over the surface semiconductor layer and on either side of insulating spacers, the semiconductor blocks having lateral facets, growth of a silicon-based layer over the semiconductor blocks, so as to fill cavities located between said facets and said insulating spacers, thermal oxidation to perform a germanium enrichment of semiconductor portions of the surface semiconductor layer disposed on either side of the spacers.Type: GrantFiled: August 24, 2021Date of Patent: May 9, 2023Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Heimanu Niebojewski, Christophe Plantier, Shay Reboh
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Patent number: 11631609Abstract: A method for manufacturing a microelectronic device from a semiconductor-on-insulator substrate, the device having active components formed in active areas of the substrate separated by isolation trenches and which are delimited by first sidewalls, the isolation trenches being filled, at least partially, with a first dielectric material, includes a step of chemically attacking a passive section of the first bottom of the isolation trenches configured to generate, at said section, a roughness quadratic mean comprised between 2 nm and 6 nm. The method also includes a step of forming a passive component covering the first dielectric material and directly above the passive section.Type: GrantFiled: July 21, 2021Date of Patent: April 18, 2023Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Heimanu Niebojewski, François Andrieu, Claire Fenouillet-Beranger
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Publication number: 20230105807Abstract: A method for manufacturing a quantum electronic circuit includes etching a semiconducting layer so as to obtain: a plurality of pillars; and a qubit layer; oxidising the flank of each pillar; forming coupling rows and coupling columns; and depositing separation layers leaving a contact surface protrude from each pillar.Type: ApplicationFiled: September 30, 2022Publication date: April 6, 2023Inventors: Heimanu NIEBOJEWSKI, Thomas BEDECARRATS, Benoit BERTRAND
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Publication number: 20230063360Abstract: A Qbit spin quantum device includes juxtaposed first and second semiconducting portions, the semiconducting portions being formed in a surface layer of a semiconductor-on-insulator type substrate and disposed on an insulating layer of the substrate, the substrate being fitted with a semiconducting support layer such that the insulating layer is arranged between the support layer and the surface layer, and several pairs of front control gates, each pair being formed respectively of first and second front control gates covering a region of the first and second semiconducting portions to form first and second quantum islands, respectively. An insulating region is provided between the first and second quantal islands to enable electrostatic coupling between the first and second quantum islands. The quantum device includes a back conductive electrode vertically aligned with a coupling insulating region and being formed of a region of metal-semiconductor material alloy arranged in the support layer.Type: ApplicationFiled: August 29, 2022Publication date: March 2, 2023Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Heimanu NIEBOJEWSKI
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Publication number: 20220416054Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.Type: ApplicationFiled: September 2, 2022Publication date: December 29, 2022Inventors: Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Lars W. Liebmann, Heimanu Niebojewski, Xuelian Zhu, Lei Sun, Hui Zang
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Patent number: 11469309Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.Type: GrantFiled: February 28, 2020Date of Patent: October 11, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Lars W. Liebmann, Heimanu Niebojewski, Xuelian Zhu, Lei Sun, Hui Zang
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Publication number: 20220231132Abstract: A method manufactures exchange gates from a starting structure including a substrate and, disposed on the substrate, a plurality of gate stacks, each gate stack including, a layer of a conductive or semiconductor material and a layer of a hard mask.Type: ApplicationFiled: January 18, 2022Publication date: July 21, 2022Inventor: Heimanu NIEBOJEWSKI
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Patent number: 11387100Abstract: A method for manufacturing a mixed substrate having, on a main face of a support substrate, a first region and a second region, includes a) providing a starting substrate which comprises an intermediate layer, consisting of the second material, and the support substrate; b) forming a mask which comprises an aperture delimiting the first region; c) forming a cavity; and d) forming the first region by epitaxially growing the first material in a single crystal form in the cavity The method includes step c1), performed before step d), of forming a protective layer, made of an amorphous material, overlaying the flank of the cavity and leaving the bottom of said cavity exposed to the external environment.Type: GrantFiled: September 10, 2020Date of Patent: July 12, 2022Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventor: Heimanu Niebojewski
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Publication number: 20220068638Abstract: Making of a transistor structure comprising in this order: forming semiconductor blocks made of SixGe1-x over the surface semiconductor layer and on either side of insulating spacers, the semiconductor blocks having lateral facets, growth of a silicon-based layer over the semiconductor blocks, so as to fill cavities located between said facets and said insulating spacers, thermal oxidation to perform a germanium enrichment of semiconductor portions of the surface semiconductor layer disposed on either side of the spacers.Type: ApplicationFiled: August 24, 2021Publication date: March 3, 2022Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Heimanu NIEBOJEWSKI, Christophe PLANTIER, Shay REBOH
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Publication number: 20220028728Abstract: The invention relates to a method for manufacturing a microelectronic device from a semiconductor-on-insulator substrate, said device comprising active components (23) formed in active areas of the substrate (10) separated by isolation trenches and which are delimited by first sidewalls (19B), said isolation trenches being filled, at least partially, with a first dielectric material, the method comprising: a step of chemically attacking a passive section (21) of the first bottom of the isolation trenches intended to generate, at said section, a roughness quadratic mean comprised between 2 nm and 6 nm, a step of forming a passive component (27), covering the first dielectric material and directly above the passive section (21).Type: ApplicationFiled: July 21, 2021Publication date: January 27, 2022Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Heimanu NIEBOJEWSKI, François ANDRIEU, Claire FENOUILLET-BERANGER