Abstract: A method for fabricating a quantum device includes, in order, forming, on a semiconductor active zone resting on a substrate, a stack having at least one layer of gate material and one or more masking layers on the layer of gate material; forming, facing the active zone, a separation trench by etching through the one or more masking layers, the trench having a bottom revealing the at least one layer of gate material; forming, in the one or more masking layers, one or more pairs of masking blocks, each pair including a second masking block facing a first masking block, the first and second masking blocks being disposed on either side of the trench; and forming, in line with each masking block and by etching the at least one layer of gate material, a gate block so as to form one or more pairs of gate blocks.

Abstract: Making of a transistor structure comprising in this order: forming semiconductor blocks made of SixGe1-x over the surface semiconductor layer and on either side of insulating spacers, the semiconductor blocks having lateral facets, growth of a silicon-based layer over the semiconductor blocks, so as to fill cavities located between said facets and said insulating spacers, thermal oxidation to perform a germanium enrichment of semiconductor portions of the surface semiconductor layer disposed on either side of the spacers.

Abstract: A method for manufacturing a microelectronic device from a semiconductor-on-insulator substrate, the device having active components formed in active areas of the substrate separated by isolation trenches and which are delimited by first sidewalls, the isolation trenches being filled, at least partially, with a first dielectric material, includes a step of chemically attacking a passive section of the first bottom of the isolation trenches configured to generate, at said section, a roughness quadratic mean comprised between 2 nm and 6 nm. The method also includes a step of forming a passive component covering the first dielectric material and directly above the passive section.

Abstract: A method for manufacturing a quantum electronic circuit includes etching a semiconducting layer so as to obtain: a plurality of pillars; and a qubit layer; oxidising the flank of each pillar; forming coupling rows and coupling columns; and depositing separation layers leaving a contact surface protrude from each pillar.

Abstract: A Qbit spin quantum device includes juxtaposed first and second semiconducting portions, the semiconducting portions being formed in a surface layer of a semiconductor-on-insulator type substrate and disposed on an insulating layer of the substrate, the substrate being fitted with a semiconducting support layer such that the insulating layer is arranged between the support layer and the surface layer, and several pairs of front control gates, each pair being formed respectively of first and second front control gates covering a region of the first and second semiconducting portions to form first and second quantum islands, respectively. An insulating region is provided between the first and second quantal islands to enable electrostatic coupling between the first and second quantum islands. The quantum device includes a back conductive electrode vertically aligned with a coupling insulating region and being formed of a region of metal-semiconductor material alloy arranged in the support layer.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: A method manufactures exchange gates from a starting structure including a substrate and, disposed on the substrate, a plurality of gate stacks, each gate stack including, a layer of a conductive or semiconductor material and a layer of a hard mask.

Abstract: A method for manufacturing a mixed substrate having, on a main face of a support substrate, a first region and a second region, includes a) providing a starting substrate which comprises an intermediate layer, consisting of the second material, and the support substrate; b) forming a mask which comprises an aperture delimiting the first region; c) forming a cavity; and d) forming the first region by epitaxially growing the first material in a single crystal form in the cavity The method includes step c1), performed before step d), of forming a protective layer, made of an amorphous material, overlaying the flank of the cavity and leaving the bottom of said cavity exposed to the external environment.

Abstract: Making of a transistor structure comprising in this order: forming semiconductor blocks made of SixGe1-x over the surface semiconductor layer and on either side of insulating spacers, the semiconductor blocks having lateral facets, growth of a silicon-based layer over the semiconductor blocks, so as to fill cavities located between said facets and said insulating spacers, thermal oxidation to perform a germanium enrichment of semiconductor portions of the surface semiconductor layer disposed on either side of the spacers.

Abstract: The invention relates to a method for manufacturing a microelectronic device from a semiconductor-on-insulator substrate, said device comprising active components (23) formed in active areas of the substrate (10) separated by isolation trenches and which are delimited by first sidewalls (19B), said isolation trenches being filled, at least partially, with a first dielectric material, the method comprising: a step of chemically attacking a passive section (21) of the first bottom of the isolation trenches intended to generate, at said section, a roughness quadratic mean comprised between 2 nm and 6 nm, a step of forming a passive component (27), covering the first dielectric material and directly above the passive section (21).

Abstract: A method for manufacturing a mixed substrate having, on a main face of a support substrate, a first region and a second region, includes a) providing a starting substrate which comprises an intermediate layer, consisting of the second material, and the support substrate; b) forming a mask which comprises an aperture delimiting the first region; c) forming a cavity; and d) forming the first region by epitaxially growing the first material in a single crystal form in the cavity The method includes step c1), performed before step d), of forming a protective layer, made of an amorphous material, overlaying the flank of the cavity and leaving the bottom of said cavity exposed to the external environment.

Abstract: A method of manufacturing a semiconductor device includes forming a composite spacer architecture over sidewalls of a sacrificial gate disposed over a semiconductor layer, and the subsequent deposition of a supplemental sacrificial gate over the sacrificial gate. A recess etch of the composite spacer architecture is followed by the formation within the recess of a sacrificial capping layer. The supplemental sacrificial gate and the sacrificial gate are removed to expose the composite spacer architecture, which is selectively etched to form a T-shaped cavity overlying a channel region of the semiconductor layer. A replacement metal gate is formed within a lower region of the T-shaped cavity, and a self-aligned contact (SAC) capping layer is formed within an upper region of the T-shaped cavity prior to metallization of the device.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

Abstract: A method of manufacturing a semiconductor device includes forming a composite spacer architecture over sidewalls of a sacrificial gate disposed over a semiconductor layer, and the subsequent deposition of a supplemental sacrificial gate over the sacrificial gate. A recess etch of the composite spacer architecture is followed by the formation within the recess of a sacrificial capping layer. The supplemental sacrificial gate and the sacrificial gate are removed to expose the composite spacer architecture, which is selectively etched to form a T-shaped cavity overlying a channel region of the semiconductor layer. A replacement metal gate is formed within a lower region of the T-shaped cavity, and a self-aligned contact (SAC) capping layer is formed within an upper region of the T-shaped cavity prior to metallization of the device.

Abstract: One integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor and an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure. In one example, the product also includes a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level above the upper surface of the first conductive source/drain contact structure, and a CB gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of the CB gate contact structure is positioned at a level that is above the first level.

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A channel region is formed that includes first and second semiconductor layers, and a gate structure is formed that is arranged over the first and second semiconductor layers. First and second source/drain regions are formed in which the second source/drain region is separated from the first source/drain region by the channel region. The first semiconductor layer is composed of a semiconductor material having a first carrier mobility, and the second semiconductor layer is composed of a semiconductor material having a second carrier mobility that is greater than the first carrier mobility of the first semiconductor layer.

Abstract: One integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor and an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure. In one example, the product also includes a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor, wherein an upper surface of the GSD contact structure is positioned at a first level that is at a level above the upper surface of the first conductive source/drain contact structure, and a CB gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of the CB gate contact structure is positioned at a level that is above the first level.

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.