Abstract: Consistent with an example embodiment, there is a semiconductor wafer substrate comprising a plurality of integrated circuits formed in arrays of rows and columns on the wafer substrate. A plurality of integrated circuits are in arrays of rows and columns on the wafer substrate; the rows and the columns have a first width. First and second saw lanes separate the integrated circuits, the first saw lanes are arranged parallel and equidistant with one another in a first direction defined by rows, and the second saw lanes are arranged parallel and equidistant with one another in a second direction defined by the columns. A plurality of process modules (PM) are on the wafer substrate, the PM modules defined in an at least one additional row/column having a second width. The at least one additional row/column is parallel to the plurality of device die in one direction.

Abstract: A semiconductor wafer (100) having a regular pattern of predetermined separation lanes (102) is provided, wherein the predetermined separation lanes (102) are configured in such a way that the semiconductor wafer is singularizable along the regular pattern.

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a plurality of integrated circuits (Ia, Ib, Ic) formed on the wafer substrate (2). Each integrated circuit (Ia, Ib, Ic) comprises an electric circuit (24) and some of the integrated circuits (Ib, Ic) comprise, in addition to their electric circuits (24), process control modules (3) as integral parts. The process control modules (3) are employed during dicing and pick-and-place to align the dicing/pick-and-place devices.

Abstract: Consistent with an example embodiment, there is a semiconductor wafer substrate comprising a plurality of integrated circuits formed in arrays of rows and columns on the wafer substrate. A plurality of integrated circuits are in arrays of rows and columns on the wafer substrate; the rows and the columns have a first width. First and second saw lanes separate the integrated circuits, the first saw lanes are arranged parallel and equidistant with one another in a first direction defined by rows, and the second saw lanes are arranged parallel and equidistant with one another in a second direction defined by the columns. A plurality of process modules (PM) are on the wafer substrate, the PM modules defined in an at least one additional row/column having a second width. The at least one additional row/column is parallel to the plurality of device die in one direction.

Abstract: A chip (1) has a substrate (2), an integrated circuit (3) provided on the substrate (2), a plurality of conductor zones (ME1, ME2, ME3, ME4, ME5) and a passivating layer (5) provided to protect the conductor zones and the integrated circuit, through-holes (6, 7) being provided in the passivating layer (5) through which chip contacts (8, 9) are accessible, wherein additional chip contacts (10, 11) and connecting conductors (12, 13) are provided on the passivating layer (5) and wherein each additional chip contact has an electrically conductive connection to a chip contact via a connecting conductor.

Abstract: Aspects of the present disclosure are directed toward methods and systems which generate a plurality of Read-Only Memory (ROM) codes. In response to generating the ROM codes, an image is generated for each of the plurality of ROM codes. The images for each of the plurality of ROM codes are mapped on a single reticle, and a wafer is provided, which includes a plurality of individual devices. The reticle is utilized, which includes an image for each of the plurality of ROM codes, to print a respective one of the images onto a respective one of the plurality of individual devices.

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a structure applied on a surface (4) of the wafer substrate (2). The structure forms a plurality of integrated circuits (1) formed on the wafer substrate (2) and the integrated circuits (1) are separated by saw lines (6, 7). The structure comprises a plurality of superposed layers (9a-9e) formed on the wafer substrate (2) and a top layer (10) formed on the superposed layers (9a-9e). The integrated circuit (1) on the wafer further comprise a plurality of alignment marks (3) intended for aligning a separating device (18) for separating the integrated circuits (1) on the wafer into individual integrated circuits (1) during a separation process, wherein the alignment marks (3) are formed from at least one of the superposed layers (9a-9e).

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2), a plurality of integrated circuits (1) formed lattice-like in rows and columns on the wafer substrate (2), and first and second saw lines (4, 5) separating the integrated circuits (1). The first saw lines (4) run parallel and equidistant with respect to each other in a first direction (x) defined by the rows and the second saw lines (5) run parallel and equidistant with respect to each other in a second direction (y)defined by the columns. The integrated circuits (1) on the wafer further comprise a plurality of process control modules (3) formed on the wafer substrate (2) such that a given process control module (3) of the plurality of process modules (3) is bounded by two consecutive first saw lines (4) as well as by two consecutive second saw lines (5).

Abstract: A semiconductor wafer (100) having a regular pattern of predetermined separation lanes (102) is provided, wherein the predetermined separation lanes (102) are configured in such a way that the semiconductor wafer is singularizable along the regular pattern.

Abstract: Integrated circuits (Ia, Ib) on a wafer (2) comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (3). Only the first integrated circuits (Ia) comprise each at least one bump (8) not contacting their relevant electric circuits (3).

Abstract: A data carrier (2) comprises a data circuit (4) arranged on a substrate (3) and data transmission unit (10) being connected to the data circuit (4). The data carrier (2) further comprises at least one strain gauge unit (7) being adapted to measure strains exerted on the substrate (3) and to transmit a deactivating signal (DE) to the data circuit (4) if the measured strains exceed a defined deactivating strain threshold. If the data circuit (4) receives the deactivating signal (DE), the data circuit (4) interrupts a data exchange with an external data reader/writer (1) via the data transmission unit (10).

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a structure applied on a surface (4) of the wafer substrate (2). The structure forms a plurality of integrated circuits (1) formed on the wafer substrate (2) and the integrated circuits (1) are separated by saw lines (6, 7). The structure comprises a plurality of superposed layers (9a-9e) formed on the wafer substrate (2) and a top layer (10) formed on the superposed layers (9a-9e). The integrated circuit (1) on the wafer further comprise a plurality of alignment marks (3) intended for aligning a separating device (18) for separating the integrated circuits (1) on the wafer into individual integrated circuits (1) during a separation process, wherein the alignment marks (3) are formed from at least one of the superposed layers (9a-9e).

Abstract: A data carrier (2) comprises a data circuit (4) arranged on a substrate (3) and data transmission means (10) being connected to the data circuit (4). The data carrier (2) further comprises at least one strain gauge means (7) being adapted to measure strains exerted on the substrate (3) and to transmit a deactivating signal (DE) to the data circuit (4) if the measured strains exceed a defined deactivating strain threshold. If the data circuit (4) receives the deactivating signal (DE), the data circuit (4) interrupts a data exchange with an external data reader/writer (1) via the data transmission means (10).

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2), a plurality of integrated circuits (1) formed lattice-like in rows and columns on the wafer substrate (2), and first and second saw lines (4, 5) separating the integrated circuits (1). The first saw lines (4) run parallel and equidistant with respect to each other in a first direction (x) defined by the rows and the second saw lines (5) run parallel and equidistant with respect to each other in a second direction (y)defined by the columns. The integrated circuits (1) on the wafer further comprise a plurality of process control modules (3) formed on the wafer substrate (2) such that a given process control module (3) of the plurality of process modules (3) is bounded by two consecutive first saw lines (4) as well as by two consecutive second saw lines (5).

Abstract: Integrated circuits (Ia, Ib) on a wafer (2) comprise first and second integrated circuits (Ia, Ib) which each include an electric circuit (3). Only the first integrated circuits (Ia) comprise each at least one bump (8) not contacting their relevant electric circuits (3).

Abstract: Integrated circuits (1) on a wafer comprise a wafer substrate (2) and a plurality of integrated circuits (1a, 1b, 1c) formed on the wafer substrate (2). Each integrated circuit (1a, 1b, 1c) comprises an electric circuit (24) and some of the integrated circuits (1b, 1c) comprise, in addition to their electric circuits (24), process control modules (3) as integral parts. The process control modules (3) are employed during dicing and pick-and-place to align the dicing/pick-and-place devices.

Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields (2) comprising a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of dicing paths (6, 8) are provided and four control module fields (A1, A2, A3, A4, B1, B2, B3, B4, C2, C4, D2, D4, E1, E3, F1, F3, G2, H1, J1) are assigned to each exposure field (2), each of which control module fields (A1, A2, A3, A4, B1, B2, B3, B4, C2, C4, D2, D4, E1, E3, F1, F3, G2, H1, J1) contains at least one optical control module (OCM-A1, OCMA2, OCM-A3, OCM-A4, OCM-B1, OCM-B2, OCM-B3, OCM-B4, OCM-C2, OCM-D4) and lies within the exposure field (2) in question and is provided in place of at least one lattice field (3) and is arranged at a mutual minimum distance (K).

Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields (2) comprises a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of dicing paths (6, 8) are provided and two control module fields (A1, A2, B1, B2, C1, D1, D2, E1, E2, F1) are assigned to each exposure field (2), each of which control module fields extends parallel to a first direction (X) and contains at least one optical control module (OCM-A1, OCM-A2, OCM-BI, OCM-B2, OCM-C1, OCM-D1, OCM-D2, OCM-E1, OCME2, OCM-F1), wherein a first control module field (OCM-A1, OCM-B1, OCM-C1, OCMD1, OCM-E1, OCM-F1) of each exposure field (2) is located between a first edge (R1, S1, T1, U1, V1, Z1) and a row of lattice fields (3) of the exposure field (2) in question and a second control module field (OCM-A2, OCM-B2, OCM-D2, OCM-E2) is located between two rows of lattice fields (3) of the exposure field (2) in question, which are arranged adjacent to a second edge (R2, S1, U2, V2), and wherein both the first contr

Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields comprises a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of saw paths (6, 8) are provided and two control module fields (A1, A2, B1, B2, C1, C2, D1, D2) are assigned to each exposure field, each of which control module fields contains at least one optical control module (OCM-A1, OCM-A2, OCM-B1, OCM-B2, OCM-C1, OCM-C2, OCM-D1, OCM-D2) and lies within the exposure field in question and comprises a plurality of control module field sections (A11, A12 . . . AIN and A21, A22 . . . A2N and B11, B12 . . . B1N and B21, B22 . . . B2N and C1N and C2N and D1N and D2N) and is distributed among several lattice grids (3), wherein each control module field section (A11 to D2N) is located in a lattice field and contains at least one control module component (10,11,12,13,14,15,16,17,18).

Abstract: In a chip (2) comprising a semiconductor body (6) and an integrated circuit (7) formed in the semiconductor body (6) and a passivation layer (14) designed to protect the integrated circuit (7) and a test contact configuration (15), the test contact configuration (15) has a test contact layer (16) lying below the passivation layer (14) and a test contact block (18) connected to the test contact layer (16), which test contact block (18) with a portion thereof projects through a hole (17) in the passivation layer (14) to the test contact layer (16) and is connected to the test contact layer (16), wherein the test contact block (18) has a contact region (20) lying above the passivation layer (14).