Abstract: A pulse width modulator (20) includes a reconfigurable counter (30) whose width is determined by mode control bits. In one embodiment, a decoder (24) decodes the mode control bits to provide decoded width control signals to the reconfigurable counter (30). The width control signals enable selected least significant counter cells (101-107) of the reconfigurable counter (30) in a binary-to-thermometer fashion. Thus, unused counter cells are disabled, reducing power. The pulse width modulator (20) also includes an output circuit (25) which provides a pulse width modulated output signal having a duty cycle determined by a proportion of a cycle of the reconfigurable counter (30) during which a comparator (23) detects that an output of the reconfigurable counter (30) has reached a value of an input number. A portion of the comparator (23) may also be disabled in response to the width control signals.

Abstract: A pulse width modulator (PWM) (20) receives a two's complement input number and separates a sign bit from remaining less significant bits. The PWM converts these bits into an unsigned number in dependence on the sign bit. A comparator (41) provides a compare output signal in response to an output of a counter (30) equaling the unsigned number. An output circuit (25) provides first and second pulse width modulated signals for a length of time determined by the output of the comparator (41) in dependence on whether the sign bit indicates a positive or negative sign. In one embodiment, the PWM (20) converts a negative two's complement number to the unsigned number by one's complementing the least significant bits, and the output circuit (25) keeps the second pulse width modulated signal active for one additional clock cycle to fully convert to two's complement form, without the need for a carry operation.