Patents by Inventor Heinrich Karrer
Heinrich Karrer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11876003Abstract: Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame assembly may include a plurality of leads, each lead including a die surface and a plating surface, and an integrated circuit die arranged on the die surface. The plating surface for each of the leads may be plated with an electrical plating. A connecting film may be applied and lead frame assembly may be singulated into individual semiconductor packages by a series of cuts through each of the plurality of leads and the electrical plating of each of the plurality of leads to a depth up to or through a portion of the connecting film to create a channel exposing lead sidewalls of each of the plurality of leads. The lead sidewalls of each of the plurality of leads may be plated with a second electrical plating and the connecting film may be removed.Type: GrantFiled: September 19, 2022Date of Patent: January 16, 2024Assignee: VISHAY GENERAL SEMICONDUCTOR, LLCInventors: Longnan Jin, Heinrich Karrer, Junfeng Liu, Huiying Ding, Thomas Schmidt
-
Patent number: 11764075Abstract: Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame may include a plurality of lead sets, each lead set including leads having a die surface and a plating surface, vias between adjacent lead sets in a first direction, and an integrated circuit die arranged on the die surface of each die lead. A mold chase may be applied to the plating surfaces, the mold chase including mold chase extensions extending into the vias between each adjacent lead set in the first direction, each mold chase extension having a peak surface. The lead frame assembly may be partially embedded in a mold encapsulation such that portions of the mold encapsulation contact the peak surfaces. The mold chase may be removed to expose the vias containing sidewalls and the plating surfaces and the sidewalls may be plated with an electrical plating.Type: GrantFiled: June 16, 2022Date of Patent: September 19, 2023Assignee: VISHAY GENERAL SEMICONDUCTOR, LLCInventors: Huiying Ding, Junfeng Liu, Longnan Jin, Heinrich Karrer, Thomas Schmidt
-
Publication number: 20230019610Abstract: Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame assembly may include a plurality of leads, each lead including a die surface and a plating surface, and an integrated circuit die arranged on the die surface. The plating surface for each of the leads may be plated with an electrical plating. A connecting film may be applied and lead frame assembly may be singulated into individual semiconductor packages by a series of cuts through each of the plurality of leads and the electrical plating of each of the plurality of leads to a depth up to or through a portion of the connecting film to create a channel exposing lead sidewalls of each of the plurality of leads. The lead sidewalls of each of the plurality of leads may be plated with a second electrical plating and the connecting film may be removed.Type: ApplicationFiled: September 19, 2022Publication date: January 19, 2023Applicant: VISHAY GENERAL SEMICONDUCTOR, LLCInventors: Longnan JIN, Heinrich KARRER, Junfeng LIU, Huiying DING, Thomas SCHMIDT
-
Publication number: 20220319869Abstract: Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame may include a plurality of lead sets, each lead set including leads having a die surface and a plating surface, vias between adjacent lead sets in a first direction, and an integrated circuit die arranged on the die surface of each die lead. A mold chase may be applied to the plating surfaces, the mold chase including mold chase extensions extending into the vias between each adjacent lead set in the first direction, each mold chase extension having a peak surface. The lead frame assembly may be partially embedded in a mold encapsulation such that portions of the mold encapsulation contact the peak surfaces. The mold chase may be removed to expose the vias containing sidewalls and the plating surfaces and the sidewalls may be plated with an electrical plating.Type: ApplicationFiled: June 16, 2022Publication date: October 6, 2022Applicant: VISHAY GENERAL SEMICONDUCTOR, LLCInventors: Huiying DING, Junfeng LIU, Longnan JIN, Heinrich KARRER, Thomas SCHMIDT
-
Patent number: 11450534Abstract: Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame assembly may include a plurality of leads, each lead including a die surface and a plating surface, and an integrated circuit die arranged on the die surface. The plating surface for each of the leads may be plated with an electrical plating. A connecting film may be applied and lead frame assembly may be singulated into individual semiconductor packages by a series of cuts through each of the plurality of leads and the electrical plating of each of the plurality of leads to a depth up to or through a portion of the connecting film to create a channel exposing lead sidewalls of each of the plurality of leads. The lead sidewalls of each of the plurality of leads may be plated with a second electrical plating and the connecting film may be removed.Type: GrantFiled: February 7, 2020Date of Patent: September 20, 2022Assignee: VISHAY GENERAL SEMICONDUCTOR, LLCInventors: Longnan Jin, Heinrich Karrer, Junfeng Liu, Huiying Ding, Thomas Schmidt
-
Patent number: 11393699Abstract: Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame may include a plurality of lead sets, each lead set including leads having a die surface and a plating surface, vias between adjacent lead sets in a first direction, and an integrated circuit die arranged on the die surface of each die lead. A mold chase may be applied to the plating surfaces, the mold chase including mold chase extensions extending into the vias between each adjacent lead set in the first direction, each mold chase extension having a peak surface. The lead frame assembly may be partially embedded in a mold encapsulation such that portions of the mold encapsulation contact the peak surfaces. The mold chase may be removed to expose the vias containing sidewalls and the plating surfaces and the sidewalls may be plated with an electrical plating.Type: GrantFiled: February 7, 2020Date of Patent: July 19, 2022Assignee: VISHAY GENERAL SEMICONDUCTOR, LLCInventors: Huiying Ding, Junfeng Liu, Longnan Jin, Heinrich Karrer, Thomas Schmidt
-
Publication number: 20210375641Abstract: Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame may include a plurality of lead sets, each lead set including leads having a die surface and a plating surface, vias between adjacent lead sets in a first direction, and an integrated circuit die arranged on the die surface of each die lead. A mold chase may be applied to the plating surfaces, the mold chase including mold chase extensions extending into the vias between each adjacent lead set in the first direction, each mold chase extension having a peak surface. The lead frame assembly may be partially embedded in a mold encapsulation such that portions of the mold encapsulation contact the peak surfaces. The mold chase may be removed to expose the vias containing sidewalls and the plating surfaces and the sidewalls may be plated with an electrical plating.Type: ApplicationFiled: February 7, 2020Publication date: December 2, 2021Applicant: VISHAY GENERAL SEMICONDUCTOR, LLCInventors: Huiying DING, Junfeng LIU, Longnan JIN, Heinrich KARRER, Thomas SCHMIDT
-
Publication number: 20210366729Abstract: Techniques and devices are disclosed for forming wettable flanks on no-leads semiconductor packages. A lead frame assembly may include a plurality of leads, each lead including a die surface and a plating surface, and an integrated circuit die arranged on the die surface. The plating surface for each of the leads may be plated with an electrical plating. A connecting film may be applied and lead frame assembly may be singulated into individual semiconductor packages by a series of cuts through each of the plurality of leads and the electrical plating of each of the plurality of leads to a depth up to or through a portion of the connecting film to create a channel exposing lead sidewalls of each of the plurality of leads. The lead sidewalls of each of the plurality of leads may be plated with a second electrical plating and the connecting film may be removed.Type: ApplicationFiled: February 7, 2020Publication date: November 25, 2021Applicant: VISHAY GENERAL SEMICONDUCTOR, LLCInventors: Longnan JIN, Heinrich KARRER, Junfeng LIU, Huiying DING, Thomas SCHMIDT
-
Patent number: 9018537Abstract: A surface-mountable electronic device free of leads has a plurality of solderable connection surfaces at its lower side, with at least one of the connection surfaces having a rectangular portion. The outline of this rectangular portion corresponds to a connection surface of the JEDEC Standard MO-236 or of any other standard according to which the respective connection surface should not extend directly up to a side edge of the lower device side. The at least one connection surface furthermore has an extension section which extends, starting from the rectangular portion, in the direction of a side edge of the lower side of the device.Type: GrantFiled: June 19, 2008Date of Patent: April 28, 2015Assignee: Vishay Semiconductor GmbHInventor: Heinrich Karrer
-
Publication number: 20090266593Abstract: A surface-mountable electronic device free of leads has a plurality of solderable connection surfaces at its lower side, with at least one of the connection surfaces having a rectangular portion. The outline of this rectangular portion corresponds to a connection surface of the JEDEC Standard MO-236 or of any other standard according to which the respective connection surface should not extend directly up to a side edge of the lower device side. The at least one connection surface furthermore has an extension section which extends, starting from the rectangular portion, in the direction of a side edge of the lower side of the device.Type: ApplicationFiled: June 19, 2008Publication date: October 29, 2009Applicant: Vishay Semiconductor GmbHInventor: Heinrich Karrer