Patents by Inventor Heinrich Korner
Heinrich Korner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8367514Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.Type: GrantFiled: January 29, 2010Date of Patent: February 5, 2013Assignee: Infineon Technologies AGInventors: Thomas Goebel, Johann Helneder, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck, Holger Torwesten
-
Patent number: 7964494Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.Type: GrantFiled: September 18, 2009Date of Patent: June 21, 2011Assignee: Infineon Technologies AGInventors: Stefan Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck
-
Publication number: 20100129977Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.Type: ApplicationFiled: January 29, 2010Publication date: May 27, 2010Inventors: Thomas Goebel, Johann Helneder, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck, Holger Torwesten
-
Patent number: 7692266Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.Type: GrantFiled: March 3, 2006Date of Patent: April 6, 2010Assignee: Infineon Technologies A.G.Inventors: Thomas Goebel, Johann Helneder, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck, Holger Torwesten
-
Publication number: 20100007027Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.Type: ApplicationFiled: September 18, 2009Publication date: January 14, 2010Inventors: Stephen Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck
-
Patent number: 7619309Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.Type: GrantFiled: February 9, 2006Date of Patent: November 17, 2009Assignee: Infineon Technologies AGInventors: Stefan Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Kôrner, Andrea Mitchell, Markus Schwerd, Martin Seck
-
Patent number: 7233053Abstract: To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric auxiliary layer (6) is deposited on a first electrode (2, 3, 5). This auxiliary layer (6) is then opened up (15) via the first electrode. Then, a dielectric layer (7) is produced, and the metal track stack (8, 9, 10) for the second electrode is then applied to the dielectric layer (6). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.Type: GrantFiled: June 10, 2004Date of Patent: June 19, 2007Assignee: Infineon Technologies AGInventors: Klaus Koller, Heinrich Körner, Michael Schrenk
-
Publication number: 20060214265Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.Type: ApplicationFiled: March 3, 2006Publication date: September 28, 2006Inventors: Thomas Goebel, Johann Helneder, Heinrich Korner, Andrea Mitchell, Markus Schwerd, Martin Seck, Holger Torwesten
-
Publication number: 20060192289Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.Type: ApplicationFiled: February 9, 2006Publication date: August 31, 2006Inventors: Stefan Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Korner, Andrea Mitchell, Markus Schwerd, Martin Seck
-
Patent number: 6958509Abstract: To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric protective layer (5) and a dielectric auxiliary layer (16) are deposited on a first electrode (2). The protective layer and the auxiliary layer (16) are then opened up (17) via the first electrode. Then, a dielectric layer (6) is produced, and the metal track stack (7, 8, 9) for the second electrode is then applied to the dielectric layer (6). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.Type: GrantFiled: June 10, 2004Date of Patent: October 25, 2005Assignee: Infineon Technologies AGInventors: Heinrich Körner, Michael Schrenk, Markus Schwerd
-
Patent number: 6940720Abstract: An integrated circuit includes an electric resistor trace, a substrate and a thermally conductive structure arranged above or below the electric resistor trace for dissipating heat from the electric resistor trace to the substrate. The present invention is based on the finding that by introducing the additional thermally conductive structure, despite the introduction of this additional thermally conductive structure requiring space at first, due to the significantly increased heat conductivity to the substrate, a smaller overall chip area for implementing integrated resistors can be obtained.Type: GrantFiled: April 25, 2003Date of Patent: September 6, 2005Assignee: Infineon Technologies AGInventors: Armin Fischer, Johann Helneder, Heinrich Körner, Markus Schwerd, Wolfgang Walter, Alexander Von Glasow
-
Publication number: 20050012223Abstract: To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric auxiliary layer (6) is deposited on a first electrode (2, 3, 5). This auxiliary layer (6) is then opened up (15) via the first electrode. Then, a dielectric layer (7) is produced, and the metal track stack (8, 9, 10) for the second electrode is then applied to the dielectric layer (6). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.Type: ApplicationFiled: June 10, 2004Publication date: January 20, 2005Inventors: Klaus Koller, Heinrich Korner, Michael Schrenk
-
Publication number: 20040256654Abstract: To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric protective layer (5) and a dielectric auxiliary layer (16) are deposited on a first electrode (2). The protective layer and the auxiliary layer (16) are then opened up (17) via the first electrode. Then, a dielectric layer (6) is produced, and the metal track stack (7, 8, 9) for the second electrode is then applied to the dielectric layer (6). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.Type: ApplicationFiled: June 10, 2004Publication date: December 23, 2004Applicant: Infineon Technologies AGInventors: Heinrich Korner, Michael Schrenk, Markus Schwerd
-
Publication number: 20040011510Abstract: An integrated circuit includes an electric resistor trace, a substrate and a thermally conductive structure arranged above or below the electric resistor trace for dissipating heat from the electric resistor trace to the substrate. The present invention is based on the finding that by introducing the additional thermally conductive structure, despite the introduction of this additional thermally conductive structure requiring space at first, due to the significantly increased heat conductivity to the substrate, a smaller overall chip area for implementing integrated resistors can be obtained.Type: ApplicationFiled: April 25, 2003Publication date: January 22, 2004Inventors: Armin Fischer, Johann Helneder, Heinrich Korner, Markus Schwerd, Wolfgang Walter, Alexander Von Glasow
-
Patent number: 5526122Abstract: In the method, the totality of the gases is conducted through an absorption cell. A reference cell contains a reference gas. The cells are optically transirradiated and a signal representing a quantity for the mass flow to be identified is generated in a detector which picks up the optical radiation emerging from the cells.Type: GrantFiled: March 14, 1994Date of Patent: June 11, 1996Assignee: Siemens AktiengesellschaftInventors: Andreas Intemann, Heinrich Korner, Konrad Hieber