Abstract: The method of nondestructive data reading from the ferroelectric memory cell supplied with the electrodes was developed. This method implies supply of reading electric voltage to the memory element electrodes with the view of generation of resilience in the ferroelectric memory cell and registration of the resilience by the field transistor with the floating gate and/or by the conductive channel made from the material with the piezoelectric properties, and according to the value of the current running through the transistor degree and character of ferroelectric cell polarization are identified. Ferroelectric memory element contains field transistor with extra piezoelement, being the memory cell. Floating gate is based on the piezoelectric material. The memory“ ”cell has three layer structure consisting of two electrodes, with the piezoelectric made from the ferroelectric material placed between the electrodes over the floating gate and transistor.

Abstract: The method of nondestructive data reading from the ferroelectric memory cell supplied with the electrodes was developed. This method implies supply of reading electric voltage to the memory element electrodes with the view of generation of resilience in the ferroelectric memory cell and registration of the resilience by the field transistor with the floating gate and/or by the conductive channel made from the material with the piezoelectric properties, and according to the value of the current running through the transistor degree and character of ferroelectric cell polarization are identified. Ferroelectric memory element contains field transistor with extra piezoelement, being the memory cell. Floating gate is based on the piezoelectric material. The memory cell has three layer structure consisting of two electrodes, with the piezoelectric made from the ferroelectric material placed between the electrodes over the floating gate and transistor.

Abstract: Systems and methodologies for programming a memory cell having a functional or selective conductive layer are provided. The functional zone can include active, and/or passive and/or barrier layers. The system includes a controller that can actively trace conditions associated with such programming. In one aspect of the present invention, by providing an external stimulus, an associated electrical or optical property associated with the memory cell is affected. Such property is then compared to a predetermined value to set/verify a programming state for the memory cell. The external stimulus can then be removed upon completion of the programming, or reduced to a verifying state to read information. The memory cell can include alternating layers of active, passive, diode, and barrier layers positioned between at least two electrodes.

Abstract: Systems and methodologies for fabrication of a memory cell or array are disclosed. The memory cell employs a functional zone with passive and active layers. Such passive and active layers facilitate electron migration, and allow a plurality of states for the memory cell. A memory device formed in accordance with the disclosed methodology can include a top-electrode formed over the functional layer, which in turn over lays a lower conductive layer.

Abstract: Disclosed are memory devices with high data reading and writing speed along with capabilities for long term storage and high information density. The memory devices allow storage of several bits of data, have fast resistance switching and require low operating voltage but at the same time allow to combine its manufacturing technology with the modern semiconductor manufacturing technology. An exemplary implementation option of the memory cell contains two continuous electrodes between which there is a multilayer functional zone consisting of one active layer, one barrier layer and one passive layer.

Abstract: The invention is in the field of Computer Engineering and can be used in memory devices for various computers, specifically in developing a universal memory system with high data reading and writing speed along with capabilities for long term storage and high information density, as well as in developing video and audio equipment of a new generation, in developing associative memory systems, and in creating synapses (electric circuit elements with programmable electric resistance) for neuronal nets. The lack of such an element holds back the development of true neuronal computers.

Abstract: Systems and methodologies for programming a memory cell having a functional or selective conductive layer are provided. The functional zone can include active, and/or passive and/or barrier layers. The system includes a controller that can actively trace conditions associated with such programming. In one aspect of the present invention, by providing an external stimulus, an associated electrical or optical property associated with the memory cell is affected. Such property is then compared to a predetermined value to set/verify a programming state for the memory cell. The external stimulus can then be removed upon completion of the programming, or reduced to a verifying state to read information.

Abstract: Systems and methodologies for fabrication of a memory cell or array are disclosed. The memory cell employs a functional zone with passive and active layers. Such passive and active layers facilitate electron migration, and allow a plurality of states for the memory cell. A memory device formed in accordance with the disclosed methodology can include a top-electrode formed over the functional layer, which in turn over lays a lower conductive layer.

Abstract: A sheet-like structure is produced from a vinyl alcohol polymer by a method wherein, in a self-cleaning multi-screw extruder, the polymer is mixed with a small amount of water, the mixture is melted, homogenized, devolatilized and finally extruded as a melt, and the extrudate is shaped in a conventional manner into the sheet-like structure.

Abstract: A cooling arrangement to be used in liquefying natural gas and in similar applications and having an incorporated cascade circuit with a fractional condensation of a cooling medium and with separation of the phases of the cooling medium, has such a lay-out and is so operated that the warming-up of the expanded cooling medium in a countercurrent evaporative heat exchange and the warming-up of the expanded cooling medium in a countercurrent supercooling heat exchange are in parallel to one another. The separated gaseous phase of the cooling medium is cooled in the countercurrent evaporative heat exchange to be at least partially condensed. The countercurrent supercooling heat exchange and the countercurrent evaporative heat exchange are thermally segregated from one another.

Abstract: A cooling arrangement to be used in liquefying natural gas and in similar applications and having an incorporated cascade circuit with a fractional condensation of a cooling medium and with separation of the phases of the cooling medium, has such a lay-out and is so operated that the warming-up of the expanded cooling medium in a countercurrent evaporative heat exchange and the warming-up of the expanded cooling medium in a countercurrent supercooling heat exchange are in parallel to one another. The separated gaseous phase of the cooling medium is cooled in the countercurrent evaporative heat exchange to be at least partially condensed. The countercurrent supercooling heat exchange and the countercurrent evaporative heat exchange are thermally segregated from one another.

Abstract: A process for liquefying gaseous substances is disclosed wherein a first fluid to be liquefied is conveyed along a first path including a portion in which it is cooled. A cooling fluid is conveyed along a second path including a first section in which it is cooled, a second section in which it exchanges heat with the first fluid so as to cool the latter, and a third section thermally separated from the aforementioned first section of the second path. A precooling fluid is conveyed along a third path including a first part also thermally separated from the aforementioned first section of the second path and wherein it exchanges heat with the cooling fluid in the third section of the second path so as to be cooled thereby. The third path further includes a second part wherein the precooling fluid exchanges heat with the cooling fluid in the first section of the second path so as to cool the same.

Abstract: A process for liquefying gaseous substances is disclosed wherein a first fluid to be liquefied is conveyed along a first path including a portion in which it is cooled. A cooling fluid is conveyed along a second path including a first section in which it is cooled, a second section in which it exchanges heat with the first fluid so as to cool the latter, and a third section thermally separated from the aforementioned first section of the second path. A precooling fluid is conveyed along a third path including a first part also thermally separated from the aforementioned first section of the second path and wherein it exchanges heat with the cooling fluid in the third section of the second path so as to be cooled thereby. The third path further includes a second part wherein the precooling fluid exchanges heat with the cooling fluid in the first section of the second path so as to cool the same.