Abstract: The present invention relates to a circuit for controlling a light emitting element, in particular an organic light emitting diode. The circuit comprises a capacitor connectable with the light emitting element, charging means for charging the capacitor and a switching means. The switching means is adapted to alternately disconnect the capacitor from the light emitting element and connect the capacitor to the light emitting element. The capacitor is alternately charged and discharged. A charging current or a discharge current from the capacitor drives the current of the light emitting element. Said charging means comprises at least one charging transistor for charging the capacitor.

Abstract: In illuminated displays with lighting elements which are driven by means of a control voltage, the voltage drop on a supply line, which supplies two or more lighting elements, is compensated for. The currents for all of the light elements which are connected to a supply line, and the known resistances are used to calculate the potential profile of the supply line for this purpose. The control voltages for the light elements are changed such that the actual potential on the supply line for each element is taken into account. Fluctuations in the brightness of the illuminated display resulting from potential differences are avoided. One element of an illuminated display has a current control means, a signal retaining means, a light emitting means and means for interrupting the current flow through the light emitting means. The control voltage is adjusted with the current flow interrupted, so that no potential differences exist on the supply line.

Abstract: A circuit for an element of a light-emitting display is proposed. The element comprises a current control means, first and second switching means, and a light-emitting means. In one embodiment, a signal holding means is provided. The arrangement of the first and second switching means of the element makes it possible to measure the electrical parameters of the current control means and of the light-emitting means during operation. A light-emitting display having a plurality of elements is furthermore proposed. The light-emitting display has a control circuit a memory. The measured values of the electrical parameters of the current control means 4 and of the light-emitting means of the elements are used to correct the control signal that is used to drive the elements. This enables a uniform brightness distribution in the case of voltage actuation and makes it possible to compensate for temporal changes in the light-emitting means.

Abstract: A variable-gain RF amplifier arrangement whose input impedance is essentially independent of the selected gain is proposed, which has a large number of selectable elementary amplifiers, with an input signal being scaled and the input impedance being set to be the same by means of switchable current limiting elements upstream of the elementary amplifiers, which are associated with the elementary amplifiers. The circuit also has a low noise level, which is largely independent of the selected gain, and good linearity. A broadcast radio receiver as well as a receiver for receiving data signals using an amplifier according to the invention are also proposed.

Abstract: The present invention relates to a full-digital implementation of a differential phase detector and to an interpolator for such a differential phase detector. According to the invention a differential phase detector for generating a tracking error signal from the digitized signals (A, B, C, D) of four photodetectors, having a multiplexer for time multiplexing the digitized signals (A, B, C, D), includes a demultiplexer/interpolator for synchronizing the samples from the time multiplexed digitized signals (A, B, C, D). The demultiplexer/interpolator favorably receives a four signal time multiplex and generates four channels at half the speed of the time multiplex.

Abstract: The invention relates to an asynchronous sample rate converter (ASRC) for the conversion of the sample rate of digital data such as audio data or video data. In the case of high over-sampling or sub-sampling factors an ASRC becomes quite complex. It is an object of the invention to provide an ASRC with a simplified design for such purposes. It is suggested to use an ASRC which has a n-tap polyphase filter, whereby a computational entity performs a polynomial computation of the filter coefficients. The attenuation at the notch frequencies is best when using a Parzen window or a quadratic window.

Abstract: A variable-gain RF amplifier arrangement whose input impedance is essentially independent of the selected gain is proposed, which has a large number of selectable elementary amplifiers, with an input signal being scaled and the input impedance being set to be the same by means of switchable current limiting elements upstream of the elementary amplifiers, which are associated with the elementary amplifiers. The circuit also has a low noise level, which is largely independent of the selected gain, and good linearity. A broadcast radio receiver as well as a receiver for receiving data signals using an amplifier according to the invention are also proposed.

Abstract: A driving circuit for a display with display elements in rows and/or columns has a shift register, through which tokens are shifted. The shift register's parallel outputs are latched and enable switch cells depending on the tokens. Control signals are supplied to the switch cells which control the output signal in terms of pulse width and/or signal shape. Buffers output the signals to a connected display. Individual or groups of buffers are connected to different supply voltages. The shift register may have more than one input in order to allow for shifting tokens in parallel, e.g. to every second output, using only one clock cycle. Further, inputs are provided for inverting the travelling direction of the tokens, inverting the shape of the signal that is output or switching all outputs to a predetermined state.

Abstract: The invention relates to an apparatus for the reproduction or recording of data or information with a photodetector and digital error signal and evaluation signal processing. The object of the invention is to provide an apparatus for the reproduction or recording of data or information which requires little outlay despite digital evaluation signal processing and a considerable capability of adaptation to different scanning speeds. The invention is based on the principle of enabling digital evaluation signal generation with an analog-to-digital converter known from audio technology, even though the data rate of the data or high-frequency signal requires an analog-to-digital converter for the radio-frequency or for the video signal band. An analog-to-digital converter for the audio frequency band can be used to generate a digital evaluation signal by the analog-to-digital converter having fed to it not the high-frequency signal directly but rather at least one envelope of the high-frequency signal.

Abstract: The high frequency oscillator comprises a reference oscillator, a phase-locked loop circuit with a phase frequency detector, a charge pump, a ring oscillator and a divider, the reference oscillator being coupled to the phase frequency detector for frequency control. The ring oscillator is a symmetrical delay cell oscillator containing two amplifiers with a dual output stage for providing I/Q output signal generation. The reference oscillator works in the range of 1.25-1.5 GHz and is a Colpitts type digital controlled frequency synthesizer with an external tank circuit for providing a low phase noise, and the dividing factor of the divider is four for providing a tuned output range of 5 to 6 GHz. The phase-locked loop circuit is integrated together with the reference oscillator into an integrated circuit, using advantageously a BICMOS Silicon/Germanium process, which is well suited for RF applications.

Abstract: The invention relates to an apparatus for the reproduction or recording of data or information with a photodetector and digital error signal and evaluation signal processing. The object of the invention is to provide an apparatus for the reproduction or recording of data or information which requires little outlay despite digital evaluation signal processing and a considerable capability of adaptation to different scanning speeds. The invention is based on the principle of enabling digital evaluation signal generation with an analog-to-digital converter known from audio technology, even though the data rate of the data or high-frequency signal requires an analog-to-digital converter for the radio-frequency or for the video signal band. An analog-to-digital converter for the audio frequency band can be used to generate a digital evaluation signal by the analog-to-digital converter having fed to it not the high-frequency signal directly but rather at least one envelope of the high-frequency signal.

Abstract: It is known for a signal-strength detection unit to be used to detect the ratio of the input signal to the wanted signal obtained after it. A disadvantage in this case is that interference elements, which are also amplified, not only corrupt the output signal of the signal-strength detection unit, but can also adversely affect the quality of the wanted signal. The invention is based on the object of providing a method for improving the wanted signal in the receiving unit of a communications system.

Abstract: The high frequency oscillator comprises a reference oscillator, a phase-locked loop circuit with a phase frequency detector, a charge pump, a ring oscillator and a divider, the reference oscillator being coupled to the phase frequency detector for frequency control. The ring oscillator is a symmetrical delay cell oscillator containing two amplifiers with a dual output stage for providing I/Q output signal generation. The reference oscillator works in the range of 1,25-1,5 GHz and is a Colpitts type digital controlled frequency synthesizer with an external tank circuit for providing a low phase noise, and the dividing factor of the divider is four for providing a tuned output range of 5 to 6 GHz. The phase-locked loop circuit is integrated together with the reference oscillator into an integrated circuit, using advantageously a BICMOS Silicon/Germanium process, which is well suited for RF applications.

Abstract: The upconverter mixer circuit comprises a Gilbert cell with an LC-resonator tuned to the output frequency of the upconverter mixer circuit, and an output buffer. In a preferred embodiment the output buffer comprises a differential amplifier being emitter degenerated with inductances for a low-pass characteristic. The LC-resonator of the Gilbert cell as well as the inductances of the output amplifier are integrated in an integrated circuit together with the other parts of the upconverter mixer circuit and provide a first selection within the integrated circuit for the subsequent stages, for example an intermediate frequency filter of a double conversion TV tuner. When the upconverter mixer circuit is operated with a strong DC-current and hard switching, which is necessary for achieving low noise, strong high frequency parasitic currents are also generated.

Abstract: The reduction of interfering influences in an LC resonant circuit with an integrated circuit is effected by including the interfering elements of the housing in the resonant circuit. This precludes the occurrence of parasitic radio-frequency oscillation modes. It also ensures good radio-frequency properties and a wide frequency tuning range.

Abstract: A method is specified for processing the output signals A to F of an optoelectronic scanner (3) in a replay or recording appliance for replaying from or recording onto an optical recording medium having the following method steps: as well as an appliance with a corresponding input circuit of a digital servo controller: first of all, the output signals A to F are supplied directly to an A/D converter (2) without the interposition of a low-pass filter, and are digitized with n-times oversampling. The digitized output signals are then supplied to a k-th order comb filter (4) by means of which undersampling of the signals to the normal sampling frequency (44.1 kHz) is carried out. After this, the undersampled output signals A' to F' of the comb filter (4) are supplied to a trimming and correction circuit (6) in which trimming and correction, of OFFSET and BALANCE are respectively carried out.

Abstract: In the case of various recording systems based on the helical-scan method for magnetic tapes, a pilot-tone principle is used for tracking control, generally using two pilot tones which are recorded on the helical tracks respectively in series of four: pilot tone F1, no pilot tone, pilot tone F2, no pilot tone. Known methods for determining the pilot-tone amplitudes use narrow-banded band filters, a control signal being generated by forming the difference between the amplitudes. On account of the weak pilot tones, this requires very narrow-banded filters with good dynamic properties.According to the invention, a quadrature mixing has the effect of converting the two pilot tones into the baseband, whereby the filtering is performed in the low-pass range and a control signal can be derived from the difference between the pilot-tone amplitudes thus determined.

Abstract: A digital detector circuit for recovering the bit timing of a data stream with a PLL includes a digital phase detector and a digital pulse length detector whose output signals are added and integrated, and the result is used for controlling the oscillator frequency. The output signal of the pulse length detector is determined by a corresponding algorithm, one slow and two fast, with direction-dependent output signals of the pulse length detector being generated.

Abstract: A sample rate converter includes a first interpolator which generates samples intermediate samples provided at a first sample rate. A second interpolator, using the intermediate samples, generates further samples at a second sample rate which are intermediate the intermediate samples. An accumulator which accumulates a value representing the ratio of the first and second sample rates, generates scale factors for performing the interpolations, and a clock signal at the second sample rate.

Abstract: A PLL system having a variable oscillator and apparatus for generating both phase and frequency error signals for controlling the variable oscillator, includes apparatus, responsive to the polarity of the frequency error signal, to selectively disconnect the frequency error signal from the variable oscillator when the PLL system approaches phase lock.