Abstract: A decoding system for an iterative decoding of a parity check code comprises a first loop circuit adapted to store log-likelihood ratio values corresponding to a plurality of received data symbols in a memory unit; a second loop circuit adapted to compute a difference between a check-to-variable log-likelihood message at a second iteration step, and a check-to-variable log-likelihood message at a first iteration step, when the first iteration step precedes the second iteration step; and an adder unit adapted to update a log-likelihood ratio value stored on the first loop circuit by adding the difference computed in the second loop circuit; wherein the first loop circuit and the second loop circuit are synchronized such that the adder unit forwards the updated log-likelihood ratio value synchronously both to the first loop circuit and to the second loop circuit.

Abstract: A decoding system for an iterative decoding of a parity check code comprises a first loop circuit adapted to store log-likelihood ratio values corresponding to a plurality of received data symbols in a memory unit; a second loop circuit adapted to compute a difference between a check-to-variable log-likelihood message at a second iteration step, and a check-to-variable log-likelihood message at a first iteration step, when the first iteration step precedes the second iteration step; and an adder unit adapted to update a log-likelihood ratio value stored on the first loop circuit by adding the difference computed in the second loop circuit; wherein the first loop circuit and the second loop circuit are synchronized such that the adder unit forwards the updated log-likelihood ratio value synchronously both to the first loop circuit and to the second loop circuit.

Abstract: An encoder encodes digital data, said encoder includes one or more component encoders, one or more interconnections between component encoders, one or more inputs and one or more outputs. The encoder is configured to carry out the following steps: combining internal input bits received via an interconnection and external input bits received via a corresponding input, to assemble a local information word, encoding the local information word such as to generate a local code word, outputting a reduced local code word and handling the same reduced local code word over to the interconnect for forwarding the same reduced local code word to another component encoder or to itself, wherein the encoder is configured to forward on each interconnect the bits of the reduced local code in parallel but with delays that are mutually different for at least a subset of the reduced local code word bits.

Abstract: Disclosed herein is an encoder for encoding digital data, said encoder comprising one or more component encoders, one or more interconnections between component encoders, one or more inputs and one or more outputs. The encoder is configured to carry out the following steps:—combining internal input bits received via an interconnection and external input bits received via a corresponding input, to assemble a local information word,—encoding the local information word such as to generate a local code word,—outputting a reduced local code word and handing the same reduced local code word over to said interconnect for forwarding said same reduced local code word via said interconnect to another component encoder or to itself, wherein said encoder is configured to forward on each interconnect the bits of the reduced local code in parallel but with delays that are mutually different for at least a subset of the reduced local code word bits.