Abstract: An integrated circuit chip having a digital memory is provided wherein direct access to at least a portion of the memory is prevented. Contact pads having coupling lines to couple the contact pads to the memory bus are provided. A security code can be programmed into a portion of the memory during wafer probe and test. When the integrated circuit chip is removed from the wafer the coupling lines between the contact pads and the memory bus are destroyed since the coupling lines are made to extend off of the chip.

Abstract: A method of automatically searching for an RF carrier uses a synthesized frequency. The synthesized frequency is generated by a voltage controlled oscillator which is part of a phase locked loop. The phase locked loop has a programmable divider which is controlled by a phase locked loop controller. The phase locked loop controller receives inputs from a frequency discriminator which is a portion of an RF receiver which is receiving the RF signals. The search is accomplished by using a frequency sweep rather than searching for a carrier at allocated frequency positions. When the search is initiated, large frequency steps are taken until a carrier signal is passed up and then the steps are decreased in size and inversed until the carrier signal is encountered again.

Abstract: A MOS latch circuit is provided which has a fast response and is sensitive to low level input clock signals. The latch circuit has two load devices which are connected to a pair of cross-coupled transistors. A controllable current source is used to control the current flow through the cross-coupled pair of transistors. A first coupling transistor is connected between the input of the cross-coupled pair of transistors and a second controllable current source. A second coupling transistor is connected between a second input of the cross-coupled pair of transistors and to the second controllable current source. The first and second coupling transistors are enabled by input data signals to the latch circuit while the first and second controllable current sources are controlled by clock signals.

Abstract: An oscillator for generating oscillation signals. The oscillation signals are initiated in response to an applied start signal and begin at a fixed predetermined phase. Hence, the oscillator is suitable for use in phase dependent timing systems to inhibit phase jitter which could otherwise occur. The oscillator includes an inverting amplifier and phase shifting feedback network for establishing and maintaining oscillations. The phase shifting feedback network includes a series coupled coil between the output and input of the inverting amplifier. A bias circuit is included for injecting direct current through the coil when oscillation is inhibited to generate a direct current magnetic field in the coil. The magnetic field ensures that, in response to the start signal, the oscillation signals begin at said fixed phase.

Abstract: An asynchronous receiver system for remotely controlling an apparatus and capable of being substantially completely constructed on a single integrated circuit chip. This system includes an input stage means for receiving during successive receiving cycles an incoming signal comprising repetitive groups of serially received frequency bursts. Each burst is composed of one of a plurality of frequencies and the frequency of the incoming signal lies between harmonic frequencies of interfering signals. A frequency divider means sequentially generates a plurality of localizer frequencies at a first output terminal and a plurality of timing signals at a second plurality of output terminals. Each timing signal is associated with one of the plurality of localizer frequencies. A mixer receives inputs from the input stage and from the first output terminal and generates sum and difference signals in response to the incoming signal and to the plurality of localizer frequencies.