Abstract: A method, device, system, and computer program product for enabling advanced control of debugging processes on a JTAG (Joint Test Action Group) IEEE 1149.1 capable device (or system under test (SUT)). Middlesoft Commander is provided within a JTAG-enabled (or JTAG) POD, which is connected to both a host system executing debugging software and the SUT. The communication between the POD and the SUT is enabled with a pair of JTAG interfaces bridging the connection between the POD and the SUT. Middlesoft Commander comprises code that enables Middlesoft Commander to convert high level commands (debug packets) received from (or generated by) the host system into JTAG commands. These JTAG commands are forwarded to the SUT. Middlesoft Commander further comprises code that enables Middlesoft Commander to convert the JTAG data received from the SUT into commands recognizable by the host system.

Abstract: A computer-implementable method, system and computer-usable medium for aiding in debugging operations of a System Under Test (SUT) through the use of an external DRONE card is presented. System test software that is running on the SUT “sets aside” debug/status information in a reserved/dedicated Peripheral Component Interface (PCI) section of system memory in the SUT. This information is communicated between the SUT and a DRONE card via a PCI bus. Debug/status information is thus accessed and manipulated by the DRONE card without disturbing (interrupting) normal operations of the SUT.

Abstract: A method, device, system, and computer program product for enabling advanced control of debugging processes on a JTAG (Joint Test Action Group) IEEE 1149.1 capable device (or system under test (SUT)). Middlesoft Commander is provided within a JTAG-enabled (or JTAG) POD, which is connected to both a host system executing debugging software and the SUT. The communication between the POD and the SUT is enabled with a pair of JTAG interfaces bridging the connection between the POD and the SUT. Middlesoft Commander comprises code that enables Middlesoft Commander to convert high level commands (debug packets) received from (or generated by) the host system into JTAG commands. These JTAG commands are forwarded to the SUT. Middlesoft Commander further comprises code that enables Middlesoft Commander to convert the JTAG data received from the SUT into commands recognizable by the host system.

Abstract: A system for integrating multiple electrical system testing functions into a single peripheral component interconnect (PCI) card. The functions of system bring-up and debug are integrated into a single PCI card, which utilizes an operating system and a set of industry standard interfaces to interconnect with standard lab instrumentation. The integrated PCI card utilizes an embedded high performance microprocessor and a compact operating system to provide control over: system-under-test (SUT) power on/off; system device sequencing via programmable General Purpose Input/Output (GPIO); system parametric control (e.g. voltage, temperature, and frequency); system parametric measurement; system debug; and remote control operation via internet interface. In one embodiment, the integrated PCI card comprises the instrumentation controller, Joint Test Action Group (JTAG) Debugger, SUT system controller, and a computer-controlled GPIO card in a single, self aware, half-slot PCI card.

Abstract: Programming or updating hardware electronic circuits without manually accessing the circuits is dislcosed. The circuit arrangement includes an EEPROM device, a FPGA device which is accessible via a computer bus system and a MUX element connected between said devices; a PROM device is arranged, inter alia, for comprising control data for proper recognition of the FPGA by the bus system. The MUX element can be controlled to read data from either the PROM device, EEPROM device, or FPGA device. In the method of the present invention, the FPGA is used to program the EEPROM with the schema received from a disk. The MUX is switched to be able to read from the EEPROM and feed the developed schema therein into the FPGA. The PROM is used to deliver the information to the FPGA, which is necessary for the PC-card to be recognized by the BIOS on a first start-up.

Abstract: An apparatus and a method for testing one or more processors. The apparatus and method provide a host computer that issues test case information. The test case information is translated from the architecture used by a host computer to the architecture required by the electronic components. The processors are then able to perform the test case.

Abstract: An apparatus and a method for testing one or more processors. The apparatus and method provide a host computer that issues test case information. The test case information is translated from the architecture used by a host computer to the architecture required by the electronic components. The processors are then able to perform the test case.

Abstract: In this circuit, video signals with a continuously increasing or decreasing amplitude are applied to the signal input of a threshold difference comparator at whose reference inputs selectively determined high and low threshold signals are applied. The output of the threshold difference comparator is applied at the first input of a threshold AND gate having a second input connected to a clock. The output of the threshold AND gate supplies a clock pulse sequence which has a duration corresponding with the time during which the input video signal has an amplitude which continuously increases or decreases from one of the threshold reference amplitudes to the other. The clock pulse sequences contained in successive measuring intervals have their respective pulses counted by a counter, and are stored in a buffer. A measurement series is performed corresponding to different focus settings, optimum focus adjustment being achieved when a minimum count of clock pulses in a clock pulse sequence is obtained.

Abstract: Method and apparatus for automatic optical inspection of a substantially two-dimensional pattern using digital image processing techniques are described. In a first processing step, all regions of a digitized stored image derived from the two-dimensional pattern are scanned for edges or lines, that is, transitions between regions having optically different characteristics. The scanned edge regions are marked in the image storage. In a subsequent second processing step all non-marked regions of the image storage are scanned and tested for the presence of permissible grey levels. A meander-shaped scanning track is used for scanning the edge or lined regions. The apparatus for implementing this method includes special latch circuitry for eliminating the further processing of marked regions, thus increasing the overall speed at which the two-dimensional pattern can be optically inspected.

Abstract: An unbalance vibrator having a shaft 2, with a flyweight 3 rigidly connected thereto, which shaft 2 is mounted in a bearing housing 1, comprises on both sides of this connecting flyweight movable flyweights 5 with flyweight bodies 6 nearly semicircular in cross section and guiding rings 7 nearly semicircular in cross section. The shaft 2 comprises a radial bore on diametrically opposite sides, into which a dog 8 is screwed, and a blind bore 11, into which a locking member 12 is retracted by action of a spring 17. The radial bore 3 and the blind bore 11 are angularly spaced by 90.degree. with respect to the center plane of the flyweight 3 rigidly connected. When the shaft 2 is rotating, the locking member 12 extends from the blind bore 11, such that the movable flyweights 5 are held between the dogs 8 and the locking members 12. The locking members 12 are subjected to hysteresis and are retracted at a rotary speed, which is lower than the loading rotary speed.