Abstract: A diagnostic arrangement is disclosed for determining the length of arbitrary shift registers not exceeding a maximum length. Knowledge of this length is an essential prerequisite for data manipulations by means of shift registers. Concerned are the reading of shift registers and the display of the contents stored in them, as well as the writing of arbitrarily selectable patterns into said shift registers.The arrangement proper includes circuitry connected to the shift register or test object for generating a test shift pattern of the length L.sub.max +K, with K.gtoreq.2, which pattern is made up of a defined bit configuration, for example, only binary ones, with a defined transition at the end facing the test object and which is shifted through the test object. Also provided is storage means of length L.sub.max +K, which is connected to the output of the test object and which, as the test shift pattern is shifted, accommodates the information of the length L.sub.x of the test object and the part L.sub.

Abstract: A priority control circuit for establishing connections between a data handling system element and a number of subsystems wherein request signals from subsystems are scanned and granted service in a sequence which is determined by their position in a priority ranking order. The scanner returns to the beginning of the order immediately after a request has been granted, the subsystem just serviced being bypassed in the next scan until all of the remaining request signals have been processed. Each time a request signal is encountered and service granted, the scanner returns to the beginning of the order, a new scan is begun and all prior requests serviced are bypassed. In the absence of any other requests or after all of the request signals have been serviced the bypassed subsystems are unlocked and a scan of all requests is begun.