Abstract: The invention relates to gain calibration in a transceiver unit (100) having a transmitter unit and a receiver unit and a feed back coupling (165) between these. A signal level measurement unit (163) measures signal levels of a feedback signal through either the receiver unit or through a signal level detector (167). A reference signal level of the feedback signal is set by adjusting the transmitter until the signal level measurement unit (163) measures a predefined value when connected through the signal level detector (167). An absolute value of the transmitter gain is then calibrated. The signal level measurement unit (163) is connected through the receiver unit and the absolute gain of the receiver is calibrated. A gain is changed either in the receiver or the transmitter unit. The relative signal level change of the feedback signal is measured and used to calibrate the gain step.

Abstract: The invention relates to gain calibration in a transceiver unit (100) having a transmitter unit and a receiver unit and a feed back coupling (165) between these. A signal level measurement unit (163) measures signal levels of a feedback signal through either the receiver unit or through a signal level detector (167). A reference signal level of the feedback signal is set by adjusting the transmitter until the signal level measurement unit (163) measures a predefined value when connected through the signal level detector (167). An absolute value of the transmitter gain is then calibrated. The signal level measurement unit (163) is connected through the receiver unit and the absolute gain of the receiver is calibrated. A gain is changed either in the receiver or the transmitter unit. The relative signal level change of the feedback signal is measured and used to calibrate the gain step.

Abstract: An apparatus for improving signal mismatch compensation between first and second RF signals comprises: at least one switch which applies a first RF signal, present on a first pathway, and a second RF signal, present on a second pathway, to respective first and second frequency mixers, during a first time period; the mixers provide a first pair of mixed first and second RF signals. Means for reversing the at least one switch, during a subsequent time period is provided so that the first RF signal is applied to the second mixer, via the second pathway, and the second RF signal is applied to the first mixer, via the first pathway. The mixers thereby provide a second pair of mixed first and second RF signals. Monitoring monitors respective first and second pairs of mixed RF signals during an interval.

Abstract: A high voltage operational amplifier receives a low voltage differential input signal at a low voltage transconductance stage (3) which provides a differential current output. An intermediate stage (5) has a differential current input coupled to the differential current output of the transconductance stage (3) via a voltage buffer stage (4) and produces a voltage output at a high voltage level but with low voltage swings providing a voltage representing the differential input signal. An interface stage (9) is coupled to receive the voltage output of the intermediate stage (5) and provides voltage and current outputs representing the voltage output of the intermediate stage (5). Output sourcing and sinking stages (6 and 7) receive the voltage and current outputs of the interface stage (9), respectively, and produce high currents representative of the differential input signal.

Abstract: A discriminator device for discriminating between two types of signal applied to an input port (EN), the first type being a binary logic signal having high and low values, and the second type of signal being a continuously variable signal or a floating voltage, the device including a voltage divider network (R1,R2) for coupling to the input port and a voltage supply (VCC) in order to provide a format signal, a second voltage divider network (R3,R4,R5) providing first and second voltage reference signals (VR1,VR2) having values intermediate the high and low values of the binary logic signal, comparators (34A, 34B) coupled to receive the format signal and the voltage reference signals, the outputs of the comparators being coupled to an output logic circuit (36-39) which provides a logic output signal of a value depending on the type of signal present at the input port.

Abstract: An integrated high voltage amplifier output stage capable of being manufactured using low voltage processes comprises a plurality of low-voltage amplifying means (8-21), such as a chain of Darlington transistor pairs, connected between a relatively high voltage source (36) and a current source (34) to provide a common output (35). A potential divider network (1-7) is connected between the high voltage source (36) and a protective high voltage FET (30) for providing low voltage inputs to each of the amplifying means. The input signal to the potential divider network (1-7) is then provided from a cascode stage made up of a low voltage transistor (29) and the high voltage FET (30), all the components being produced by a low voltage process.

Abstract: A noise-tolerant transition detector circuit (2) for detecting when an input signal rises above a first value (V2) and falls below a second value (V1) comprising: comparator means (12, 14) which produces a first output signal when the input signal rises above the first value and a second output signal when the input signal falls below the second value; and bistable means (20) which is set to its first stable state in response to the comparator means first output signal and which is set to its second stable state in response to the comparator means second output signal.Noise may be further reduced by using further bistable means (26) and pulse-forming means (28, 30) may also be employed.

Abstract: A fixed frequency, variable duty cycle voltage regulator having a precision reference voltage source is provided. The reference voltage source has a variable temperature coefficient. The output of the precision reference voltage source is combined by a digitally switched attenuator to provide a staircase waveform to a comparator. This variable staircase waveform is compared against the output of an alternator. The comparator sets the output of a flip-flop to an off state when the staircase waveform goes below the output from the alternator. This removes the drive from a current switch which switches off the current flow through the field coil of the alternator.

Abstract: In an n-type base island are provided a p-type emitter stripe and a p-type output collector stripe, with one or more intermediate control collector stripes for switching the current of the output collector. The pattern of control collector stripes can provide AND functions, OR functions or combinations thereof in a single logic element in a single base island. Each output is provided with an npn current reversal transistor in a separate island and if more than one input is to be operated by the output of a logic element, decoupling and fan-out capability are provided by vertical pnp transistors driven by the inverter transistors, which do not require an island completely separate from the inverter transistor, although an isolating barrier stripe can be helpful. A bistable flipflop and a frequency divider cell are shown to illustrate the use of these logic structures. The decoupling referred to can be provided without fan-out amplification by means of diodes.