Abstract: A method of making a multilayer thin film structure on the surface of a dielectric substrate which includes the steps of:a. forming a multilayer thin film structure including the steps of:applying a first layer of dielectric polymeric material on the surface of a dielectric substrate,applying a second layer of dielectric polymeric material over the first layer of polymeric material wherein the second polymeric material is photosensitive,imagewise exposing and developing the second polymeric material to form a feature therein, the second layer feature in communication with at least one feature formed in the first polymeric material; andb. filling the features in the entire multilayer structure simultaneously with conductive material.Preferably, the first layer feature is a via and the second layer feature is a capture pad or wiring channel. Also disclosed is a multilayer thin film structure made by this method.

Abstract: The present invention provides a packaging semiconductor structure and method for obtaining same. The structure is comprised of at least one level of dielectric and metallurgy layers. The at least one level is comprised of a wiring metallurgy plane and a "through-via" plane of interconnecting metallurgy in association with both one and two layers of polymeric dielectric materials. The self-alignment method of fabrication of the level provides a streamlined technique wherein stringent masking and alignment requirements are relaxed, undue processing such as at least one polishing step is eliminated and a structure having adhesive integrity is fabricated.

Abstract: Disclosed is a ceramic substrate having a protective coating on at least one surface thereof which includes:a ceramic substrate having at least one electrically conductive via extending to a surface of the substrate;an electrically conductive I/O pad electrically connected to at least one of the vias;an I/O pin brazed to the I/O pad, the brazed pin having a braze fillet; anda protective layer of polymeric material fully encapsulating the I/O pad, wherein the layer of polymeric material protects the I/O pad from corrosion.

Abstract: The present invention provides a packaging semiconductor structure and method for obtaining same. The structure is comprised of at least one level of dielectric and metallurgy layers. The at least one level is comprised of a wiring metallurgy plane and a "through-via" plane of interconnecting metallurgy in association with both one and two layers of polymeric dielectric materials. The self-alignment method of fabrication of the level provides a streamlined technique wherein stringent masking and alignment requirements are relaxed, undue processing such as at least one polishing step is eliminated and a structure having adhesive integrity is fabricated.