Abstract: The present invention provides a CAM (content addressable memory) apparatus having: a first memory device (10) with a word line input (WL) and at least one storage node (12; 13) for storing a first bit of a data word; a second memory device (11) with a word line input (WL) and at least one storage node (14; 15) for storing a second bit of a data word; and a comparator device (16) for comparing the first and second stored bits with two precoded comparison bits fed via four inputs (20; 21; 22; 23) and for driving a hit node (17) in the event of the first stored bit corresponding to the first comparison bit and the second stored bit corresponding to the second comparison bit.

Abstract: One embodiment provides a content addressable memory cell having a first memory cell which is electrically connected to a comparator unit. The comparator unit is constructed from at least eight transistors, at least four transistors being arranged in a first circuit part and at least four transistors being arranged in a second circuit part and each of the circuit parts having at least two circuit branches.

Abstract: A carry ripple adder contains five first inputs for accepting five input bits having equal significance w that are to be summed and two second inputs for accepting two carry bits having the significance w. It also contains an output for a sum bit having the significance w and two outputs for two carry bits having the significances 2w and 4w.

Abstract: A method for optimizing the layout of cells of an integrated circuit includes providing a cell-based network list with references to cell definitions with parameterizable dimensions, calculating a layout of an integrated circuit using the cell-based network list, extracting a primary network list from the layout, optimizing the component dimensions of at least some of the components of the integrated circuit using at least one predetermined optimization parameter and a simulation using the primary network list, creating an optimized secondary network list using the results of the component optimization, and automatically modifying the layout with respect to cell dimensions using a secondary network list.