Abstract: The present invention relates to a digital communication device comprising interconnected modules for processing and/or handling received data signals, wherein said interconnected modules each comprise means for monitoring (monitoring means) said data signal and for generating an output data signal having a predetermined signal status (squelched data signal) if said data signal is erroneous. The invention also relates to a method for processing a data signal within a communication device, preferably a communication device according to the present invention.

Abstract: An optical cross-connect (OCX), which is designed for the switching of so-called Optical Channels of different multiplex levels with respectively defined bit rates, has a number of input/output ports (I/O) which are respectively adapted to transmit and receive communication signals of a particular multiplex level, and a switching matrix (S) which is connected to the input/output ports (I/O). The switching matrix (S) is a space switching matrix which is transparent for communication signals of all multiplex levels. In order to provide the interface between the individual multiplex levels, the cross-connect (OCX) has at least one multiplexer (MUX), which is also connected to the switching matrix (S).

Abstract: An optical cross-connect (OCX), which is designed for switching so-called optical channels of different multiplex levels with respectively defined bit rates, comprises a number of input/output ports (IO1, IO2, IO3) which are respectively adapted for transmitting and receiving communication signals of a given multiplex level. The cross-connect further comprises, for each multiplex level, a separate space switching matrix (S1, S2, S3) which is adapted to that multiplex level. The individual switching matrices (S1, S2, S3) are interconnected via multiplexers (MUX1, MUX2).

Abstract: An optical cross-connect (OCX), which is designed for the switching of so-called Optical Channels of different multiplex levels with respectively defined bit rates, has a number of input/output ports (IO1, IO2, IO3) which are respectively adapted to transmit and receive communication signals of a particular multiplex level. The cross-connect furthermore has a space switching matrix (S) which is adapted to switch communication signals of the lowest multiplex level.

Abstract: Parallel working additive scramblers produce a predetermined pseudorandom sequence of length L in a word generator, which consists of an N-stage shift register. To obtain more than N parallel located pseudorandom sequences, the word generator is connected to a network in which, in addition to the pseudorandom sequences created by modulo-2 addition, other pseudorandom sequences are created with a different phase relation. Performing the linkage operations limits the maximum bit rate sequence that can be transmitted. The entire pseudorandom sequence is stored in a memory (S). The desired pseudorandom sequence is produced in a circular storage (RS) by means of shifting operations. The circular storage (RS) is in the form of a feedback shift register (SR) and is used as the memory (S), in which each of the outputs is connected to an input of an EXOR-gate, in which a pseudorandom sequence is modulo-2 added with a partial stream of a parallelized serial data stream.

Abstract: Information transmission networks with a synchronous hierarchy of digital signals, require that digital signals of the plesiochronous hierarchy are to be inserted into multiplex elements with prescribed pulse frames. The pulse frame is structured word by word, but a larger or smaller number of bits must be stuffed in a bitwise manner at the end of specific words. A multiplexer for the resolution of such a pulse frame and elimination of the stuffing bits are provided. The multiplexer operates in a word-by-word manner and repeats the replaced bits of the digital signal at the starting bits of the next word. In a similar manner, the demultiplexer also operates word by word and eliminates the stuffing bits contained in a word, by overwriting them in an elastic memory during writing-in of the next word. In both cases, this is achieved by a controllable shift of memory addresses.