Abstract: Shallow junction field effect transistors are made by a low temperature process comprising ion implanting source/drain regions through a buffer layer in two steps, the first an ion implant at high dosage and low energy and the second an ion implant at low dosage and high energy. Ion implantation through the buffer layer avoids crystallographic damage to the silicon substrate. By grading the sidewall spacers of the gate electrode, more or fewer ions can be implanted through the spacer foot to ensure continuity between the source/drain regions and the channel region under the gate electrode.

Abstract: In a method of determining the possible formation of crystalline defects in a body of a semiconductor material during the process of fabricating integrated circuits in the body, at least one body is subjected to a full fabrication process to form completed integrated circuits in the body which can be electrically tested to determine whether the operation of the integrated circuit is adversely affected by the formation of crystalline defects. Test structures, each of which is only a portion of the complete integrated circuit, are formed during the formation of the complete circuit but are fabricated using only a group of a limited number of the steps of the fabrication process used to fabricate the complete integrated circuit with various ones of the test structures being subjected to different ones of the steps of the group of steps. The test structures may be formed on the same body as the complete circuit or on additional bodies.

Abstract: Shallow junction field effect transistors are made by a low temperature process comprising ion implanting source/drain regions through a buffer layer in two steps, the first an ion implant at high dosage and low energy and the second an ion implant at low dosage and high energy. Ion implantation through the buffer layer avoids crystallographic damage to the silicon substrate.By grading the sidewall spacers of the gate electrode, more or fewer ions can be implanted through the spacer foot to ensure continuity between the source/drain regions and the channel region under the gate electrode.