Abstract: A content addressable memory (CAM) (30) and a method of using it to sequentially match tags stored in the CAM to a target tag. The CAM (30) has a tag memory (20) comprised of tag cells (10, 10a) and also has a data cache. Each tag cell (10, 10a) is structured like a conventional RAM cell for storing a bit of data but also has a multiplexing switch (16) at its output. The multiplexing switch (16) applies a signal representing the tag cell's contents to a readline (15). A tag compare circuit (25) external to tag memory (20). On each readline, tag compare circuit (25) compares a bit from each cell (10, 10a) in a selected column to a bit of the target address. This cycle is repeated for all bits of the target address and successive columns of the tag memory unless terminated by a mismatch for all cells (10, 10a) in a column. The tag compare circuit (25) has logic circuitry that maintains a “hit” output signal.