Patents by Inventor Hejin Liu
Hejin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150357266Abstract: A packaged semiconductor device is assembled using a first lead frame upon which a die is mounted and encapsulated and a second lead frame that provides bent leads for the device. By using two different lead frames, an array of the first lead frames can be configured with more lead frames for more devices than a comparably sized lead frame array of the prior art because the first lead frame array does not need to provide the leads for the packaged devices. Instead, the leads are provided by the second lead frame array, which can be attached to the first lead frame array after the dies have been mounted and encapsulated on the first lead frame array.Type: ApplicationFiled: November 26, 2014Publication date: December 10, 2015Inventors: Huan Wang, Hejin Liu, Weiping Sun
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Patent number: 9209119Abstract: A packaged semiconductor device is assembled using a first lead frame upon which a die is mounted and encapsulated and a second lead frame that provides bent leads for the device. By using two different lead frames, an array of the first lead frames can be configured with more lead frames for more devices than a comparably sized lead frame array of the prior art because the first lead frame array does not need to provide the leads for the packaged devices. Instead, the leads are provided by the second lead frame array, which can be attached to the first lead frame array after the dies have been mounted and encapsulated on the first lead frame array.Type: GrantFiled: November 26, 2014Date of Patent: December 8, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Huan Wang, Hejin Liu, Weiping Sun
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Patent number: 8907464Abstract: A three dimensional (3D) package includes a helix substrate having a columnar part including a top surface, a bottom surface and a sidewall, and a plurality of steps arranged along the sidewall of the columnar part in the form of a helix. Semiconductor integrated circuits (dies) may be attached on supporting surfaces of the steps. The columnar part, the steps and the dies can be covered with a mold compound. I/Os are formed at either the sides of the steps and/or the top and/or bottom of the columnar part.Type: GrantFiled: March 22, 2013Date of Patent: December 9, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Huan Wang, Meiquan Huang, Hejin Liu
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Publication number: 20140146497Abstract: A three dimensional (3D) package includes a helix substrate having a columnar part including a top surface, a bottom surface and a sidewall, and a plurality of steps arranged along the sidewall of the columnar part in the form of a helix. Semiconductor integrated circuits (dies) may be attached on supporting surfaces of the steps. The columnar part, the steps and the dies can be covered with a mold compound. I/Os are formed at either the sides of the steps and/or the top and/or bottom of the columnar part.Type: ApplicationFiled: March 22, 2013Publication date: May 29, 2014Inventors: Huan Wang, Meiquan Huang, Hejin Liu
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Patent number: 8524529Abstract: An electrical connection includes a first wire having one end stitch bonded to a surface, such as the lead finger of a lead frame or the connection pad of a substrate. A second wire has a first end attached to the surface on a first side of the first wire and a second end attached to the surface on a second, opposing side of the first wire. The second wire acts as a brace that prevents the first wire from lifting off of the surface. If necessary, a third wire can be added that, like the second wire, acts as a brace to prevent the first wire from lifting off of the surface.Type: GrantFiled: June 28, 2011Date of Patent: September 3, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Meiquan Huang, Hejin Liu, Hanmin Zhang
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Patent number: 8496158Abstract: A method for monitoring free air ball (FAB) formation during a wire bonding process includes attaching a dummy bond wire to an unused location on a first surface of a semiconductor chip carrier, extending the dummy bond wire a predetermined distance from the first surface such that a tip of the dummy bond wire is spaced from the first surface, and forming a dummy FAB at the tip of the bond wire. A profile of the dummy FAB is inspected with an imaging unit to identify any defects in the dummy FAB. An alarm is triggered and the wire bonding process is halted if the dummy FAB is defective so that bonding parameters may be adjusted. The wire bonding process is restarted after the bonding parameters have been adjusted.Type: GrantFiled: September 6, 2012Date of Patent: July 30, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Fei Zong, Guoliang Gong, Meiquan Huang, Hejin Liu
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Publication number: 20130119114Abstract: A method for monitoring free air ball (FAB) formation during a wire bonding process includes attaching a dummy bond wire to an unused location on a first surface of a semiconductor chip carrier, extending the dummy bond wire a predetermined distance from the first surface such that a tip of the dummy bond wire is spaced from the first surface, and forming a dummy FAB at the tip of the bond wire. A profile of the dummy FAB is inspected with an imaging unit to identify any defects in the dummy FAB. An alarm is triggered and the wire bonding process is halted if the dummy FAB is defective so that bonding parameters may be adjusted. The wire bonding process is restarted after the bonding parameters have been adjusted.Type: ApplicationFiled: September 6, 2012Publication date: May 16, 2013Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Fei ZONG, Guoliang GONG, Meiquan HUANG, Hejin LIU
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Publication number: 20120326288Abstract: A method of assembling a semiconductor device includes providing a conductive lead frame panel and selectively half-etching a top side of the lead frame panel to provide a pin pads. A flip chip die is attached and electrically connected to the pin pads and then the lead frame panel and die are encapsulated with molding compound. A second selective half etching step is performed on a backside of the lead frame panel to form a plurality of separate input/output pins. The side walls of each input/output pin include arcuate surfaces in cross-section.Type: ApplicationFiled: June 6, 2012Publication date: December 27, 2012Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Meiquan Huang, Hejin Liu, Zhijie Wang, Dehong Ye, Hanmin Zhang
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Patent number: 8288847Abstract: A dual die semiconductor package has a grid array of electrical contacts on a bottom surface of a substrate. There is a first semiconductor die with a base surface mounted to an upper surface of the substrate and the first semiconductor die has first die upper surface external electrical connection pads on an upper surface that are electrically connected to respective electrical contacts of the grid array. There is also a second semiconductor die with a base surface mounted to an upper surface of a lead frame flag. There are second die upper surface external electrical connection pads on an upper surface of the second semiconductor die. The dual die semiconductor package includes leads and at least some of the leads are electrically connected to respective pads that provide the second die upper surface external electrical connection pads. A package body at encloses the first semiconductor die and the second semiconductor die.Type: GrantFiled: July 6, 2010Date of Patent: October 16, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Meiquan Huang, Hejin Liu, Wenjian Xu, Dehong Ye
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Publication number: 20120077316Abstract: An electrical connection includes a first wire having one end stitch bonded to a surface, such as the lead finger of a lead frame or the connection pad of a substrate. A second wire has a first end attached to the surface on a first side of the first wire and a second end attached to the surface on a second, opposing side of the first wire. The second wire acts as a brace that prevents the first wire from lifting off of the surface. If necessary, a third wire can be added that, like the second wire, acts as a brace to prevent the first wire from lifting off of the surface.Type: ApplicationFiled: June 28, 2011Publication date: March 29, 2012Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Meiquan HUANG, Hejin Liu, Hanmin Zhang