Abstract: A system includes an image sensor structure and a flow cell. The image sensor structure includes an image layer disposed over a base substrate. A device stack is disposed over the image layer. A bond pad is disposed in the device stack. A passivation stack is disposed over the device stack and the bond pad. An array of nanowells is disposed in a top layer of the passivation stack. A through-silicon via (TSV) is in electrical contact with the bond pad. The TSV extends through the base substrate. A redistribution layer (RDL) is disposed on a bottom surface of the base substrate. The RDL is in electrical contact with the TSV. The flow cell is disposed upon the top layer of the passivation stack to form a flow channel therebetween. The flow channel is disposed over the array of nanowells and the bond pad.

Abstract: In one embodiment, a sample surface of a biosensor includes pixel areas and holds a plurality of clusters during a sequence of sampling events such that the clusters are distributed unevenly over the pixel areas. In another embodiment, a biosensor has a sample surface that includes pixel areas and an array of wells overlying the pixel areas, the biosensor including two wells and two clusters per pixel area. The two wells per pixel area include a dominant well and a subordinate well. The dominant well has a larger cross section over the pixel area than the subordinate well. In yet another embodiment, an illumination system is coupled to a biosensor that illuminates the pixel areas with different angles of illumination during a sequence of sampling events, including, for a sampling event, illuminating each of the wells with off-axis illumination to produce asymmetrically illuminated well regions in each of the wells.

Abstract: A biosensor for base calling is provided. The biosensor comprises a sampling device, which includes a sample surface that has an array of pixel areas and a solid-state imager that has an array of sensors. Each sensor generates pixel signals in each base calling cycle. Each pixel signal represents light gathered in one base calling cycle from one or more clusters in a corresponding pixel area of the sample surface. The biosensor further comprises a signal processor configured for connection to the sampling device. The signal processor receives and processes the pixel signals from the sensors for base calling in a base calling cycle, and uses the pixel signals from fewer sensors than a number of clusters base called in the base calling cycle. The pixel signals from the fewer sensors include at least one pixel signal representing light gathered from at least two clusters in the corresponding pixel area.

Abstract: Light detection devices and related methods are provided. The devices may comprise a reaction structure for containing a reaction solution with a relatively high or low pH and a plurality of reaction sites that generate light emissions. The devices may comprise a device base comprising a plurality of light sensors, device circuitry coupled to the light sensors, and a plurality of light guides that block excitation light but permit the light emissions to pass to a light sensor. The device base may also include a shield layer extending about each light guide between each light guide and the device circuitry, and a protection layer that is chemically inert with respect to the reaction solution extending about each light guide between each light guide and the shield layer. The protection layer prevents reaction solution that passes through the reaction structure and the light guide from interacting with the device circuitry.

Abstract: An electronic assembly, comprising a carrier wafer having a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising a wafer contact pad on the top wafer surface; said carrier wafer comprising a through-wafer cavity joining the top and bottom wafer surfaces; a component chip having a component chip top surface, a component chip bottom surface and component chip side surfaces, the component chip being held in said through-wafer cavity by an attachment material attaching at least one wall of the through-wafer cavity to at least one of the component chip bottom surface and a component chip side surface; said component chip comprising at least one component contact pad on said component chip top substrate; a first conductor connecting said wafer contact pad and said component contact pad.

Abstract: A method and a semiconductor device for incorporating defect mitigation structures are provided. The semiconductor device comprises a substrate, a defect mitigation structure comprising a combination of layers of doped or undoped group IV alloys and metal or non-metal nitrides disposed over the substrate, and a device active layer disposed over the defect mitigation structure. The defect mitigation structure is fabricated by depositing one or more defect mitigation layers comprising a substrate nucleation layer disposed over the substrate, a substrate intermediate layer disposed over the substrate nucleation layer, a substrate top layer disposed over the substrate intermediate layer, a device nucleation layer disposed over the substrate top layer, a device intermediate layer disposed over the device nucleation layer, and a device top layer disposed over the device intermediate layer.

Abstract: A method and a semiconductor device for incorporating defect mitigation structures are provided. The semiconductor device comprises a substrate, a defect mitigation structure comprising a combination of layers of doped or undoped group IV alloys and metal or non-metal nitrides disposed over the substrate, and a device active layer disposed over the defect mitigation structure. The defect mitigation structure is fabricated by depositing one or more defect mitigation layers comprising a substrate nucleation layer disposed over the substrate, a substrate intermediate layer disposed over the substrate nucleation layer, a substrate top layer disposed over the substrate intermediate layer, a device nucleation layer disposed over the substrate top layer, a device intermediate layer disposed over the device nucleation layer, and a device top layer disposed over the device intermediate layer.