Abstract: A pipeline Fast Fourier Transform (“FFT”) architecture for a programmable device is described. A first Radix-2 butterfly stage is coupled to receive a first input, configured to provide a first output responsive thereto, and configured to truncate at least one Least Significant Bit of the first output. A delay and swap stage is coupled to receive the first output and configured to provide a second output. A second Radix-2 butterfly stage is coupled to receive the second output and a second input, configured to provide a third output responsive thereto, and configured to truncate at least one Most Significant Bit of the third output. The first Radix-2 butterfly stage and the second Radix-2 butterfly stage are implemented in digital signal processing slices of a programmable device.

Abstract: Various approaches for performing a fast-Fourier transform (FFT) of N input data elements using a radix K decomposition of the FFT are disclosed (K>=2, and N>=8). In one approach, N/K input data elements are written to respective ones of K addressable memories, and N/K*logK N passes are performed on the input data. Each pass includes reading K data elements in parallel from the K addressable memories using the respectively generated addresses, the K data elements being in a first order corresponding to the respective memories; permuting the first order of K data elements into a second order of K data elements; performing a radix K calculation on the second order of K data elements, resulting in corresponding result data elements in the second order; permuting the second order of K result data elements into the first order; and writing the K result data elements in parallel to the corresponding K addressable memories using the respective addresses.