Abstract: A method of processing a workpiece is disclosed, where the interior surfaces of the plasma chamber are first coated using a conditioning gas that contains the desired dopant species. A working gas, which does not contain the desired dopant species, is then introduced and energized to form a plasma. This plasma is used to sputter the desired dopant species from the interior surfaces. This dopant species is deposited on the workpiece. A subsequent implant process may then be performed to implant the dopant into the workpiece. The implant process may include a thermal treatment, a knock in mechanism, or both.

Abstract: A method of processing a workpiece is disclosed, where the interior surfaces of the plasma chamber are first coated using a conditioning gas that contains the desired dopant species. A working gas, which does not contain the desired dopant species, is then introduced and energized to form a plasma. This plasma is used to sputter the desired dopant species from the interior surfaces. This dopant species is deposited on the workpiece. A subsequent implant process may then be performed to implant the dopant into the workpiece. The implant process may include a thermal treatment, a knock in mechanism, or both.

Abstract: A method of conformally doping a device on a semiconductor workpiece is disclosed. An oxide layer is applied to all surfaces of the device. Further, the thickness of the oxide layer on each surface is proportional to the energy that ions impact that particular surface. For example, ions strike the horizontal surfaces at nearly a normal angle and penetrate more deeply into the workpiece than ions striking the vertical surfaces. After creating an oxide layer that has a variable thickness, a subsequent dopant implant is performed. While ions strike the horizontal surfaces with more energy, these ions pass through a thicker oxide layer to penetrate the workpiece. In contrast, ions strike the vertical surfaces with less energy, but traverse a much thinner oxide layer to penetrate the workpiece. The result is a conformally doped device.

Abstract: Techniques for plasma processing a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a method comprising introducing a feed gas proximate to a plasma source, where the feed gas may comprise a first and second species, where the first and second species have different ionization energies; providing a multi-level RF power waveform to the plasma source, where the multi-level RF power waveform has at least a first power level during a first pulse duration and a second power level during a second pulse duration, where the second power level may be different from the first power level; ionizing the first species of the feed gas during the first pulse duration; ionizing the second species during the second pulse duration; and providing a bias to the substrate during the first pulse duration.

Abstract: A novel technique for manufacturing bit patterned media is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for manufacturing bit pattern media. The technique, which may be realized as a method comprising: forming a non-catalysis region on a first portion of a catalysis layer; forming a non-magnetic separator on the non-catalysis region; and forming a magnetic active region on a second portion of the catalysis layer adjacent to the first portion of the catalysis layer.

Abstract: A method of processing a substrate having horizontal and non-horizontal surfaces is disclosed. The substrate is implanted with particles using an ion implanter. During the ion implant, due to the nature of the implant process, a film may be deposited on the surfaces, wherein the thickness of this film is thicker on the horizontal surfaces. The presences of this film may adversely alter the properties of the substrate. To rectify this, a second process step is performed to remove the film deposited on the horizontal surfaces. In some embodiments, an etching process is used to remove this film. In some embodiments, a material modifying step is used to change the composition of the material comprising the film. This material modifying step may be instead of, or in addition to the etching process.

Abstract: Various methods of utilizing the physical and chemical property differences between amorphized and crystalline silicon are used to create masks that can be used for subsequent implants. In some embodiments, the difference in film growth between amorphous and crystalline silicon is used to create the mask. In other embodiments, the difference in reflectivity or light absorption between amorphous and crystalline silicon is used to create the mask. In other embodiments, differences in the characteristics of doped and undoped silicon is used to create masks.

Abstract: A novel, technique: for manufacturing bit patterned media is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for manufacturing hit pattern media. The technique, which may be realized as a method comprising: forming a non-catalysis region on a first portion of a catalysis layer; forming a non-magnetic separator on the non-catalysis region; and forming a magnetic active region on it second portion of the catalysis layer adjacent to the first portion of the catalysis layer.

Abstract: A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing a series of ion implantation steps at predetermined implant energies to implant carbon ions deep within the semiconductor structure to create a strain layer. The strain layer is annealed using a millisecond anneal process. Subsequent ion implantation steps are used to dope the source/drain region, and the source/drain extension with phosphorus ions, so that the doped regions remain above the strain layer. A second millisecond anneal step activates the source/drain region and the source/drain extension. The strain layer enhances carrier mobility within a channel region of the semiconductor structure, while also preventing diffusion of P within the structure.

Abstract: Techniques for plasma processing a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a method comprising introducing a feed gas proximate to a plasma source, where the feed gas may comprise a first and second species, where the first and second species have different ionization energies; providing a multi-level RF power waveform to the plasma source, where the multi-level RF power waveform has at least a first power level during a first pulse duration and a second power level during a second pulse duration, where the second power level may be different from the first power level; ionizing the first species of the feed gas during the first pulse duration; ionizing the second species during the second pulse duration; and providing a bias to the substrate during the first pulse duration.

Abstract: Various methods of utilizing the physical and chemical property differences between amorphized and crystalline silicon are used to create masks that can be used for subsequent implants. In some embodiments, the difference in film growth between amorphous and crystalline silicon is used to create the mask. In other embodiments, the difference in reflectivity or light absorption between amorphous and crystalline silicon is used to create the mask. In other embodiments, differences in the characteristics of doped and undoped silicon is used to create masks.

Abstract: A method of processing a substrate having horizontal and non-horizontal surfaces is disclosed. The substrate is implanted with particles using an ion implanter. During the ion implant, due to the nature of the implant process, a film may be deposited on the surfaces, wherein the thickness of this film is thicker on the horizontal surfaces. The presences of this film may adversely alter the properties of the substrate. To rectify this, a second process step is performed to remove the film deposited on the horizontal surfaces. In some embodiments, an etching process is used to remove this film. In some embodiments, a material modifying step is used to change the composition of the material comprising the film. This material modifying step may be instead of, or in addition to the etching process.

Abstract: A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing one or more cold-carbon or molecular carbon ion implantation steps to implant carbon ions within the semiconductor structure to create strain layers on either side of a channel region. Raised source/drain regions are then formed above the strain layers, and subsequent ion implantation steps are used to dope the raised source/drain region. A millisecond anneal step activates the strain layers and the raised source/drain regions. The strain layers enhances carrier mobility within a channel region of the semiconductor structure, while the raised source/drain regions minimize reduction in strain in the strain layer caused by subsequent implantation of dopant ions in the raised source/drain regions.

Abstract: A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing a series of ion implantation steps at predetermined implant energies to implant carbon ions deep within the semiconductor structure to create a strain layer. The strain layer is annealed using a millisecond anneal process. Subsequent ion implantation steps are used to dope the source/drain region, and the source/drain extension with phosphorus ions, so that the doped regions remain above the strain layer. A second millisecond anneal step activates the source/drain region and the source/drain extension. The strain layer enhances carrier mobility within a channel region of the semiconductor structure, while also preventing diffusion of P within the structure.

Abstract: The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, cavities are formed in the areas with and without vias. The depth of the cavities formed in the areas with vias will extend deeper into the substrate than the cavities formed in areas without vias. Such occurs because the polymer deposits unevenly along the surface of the substrate and more specifically, more thinly in areas with underlying depressions. Once filled with a conductive material, cavities which extend more deeply into the substrate, which were formed in areas with vias, become inductors, and the cavities which extend less deeply into the substrate, which were formed in areas without vias, become interconnects.

Abstract: Disclosed are methods and systems for etching dielectric layers in a high density plasma etcher. A method includes providing a wafer having a photoresist mask over a dielectric layer in order to define at least one contact via hole or open area that is electrically interconnected down to the silicon substrate of the wafer. The method then proceeds to inserting the wafer into the high density plasma etcher and pulsed application a TCP power source of the high density plasma etcher. The pulsed application includes ascertaining a desired etch performance characteristic, which includes photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source. Then, selecting a duty cycle of the pulsed application of the TCP source and scaling a peak power of the pulsed application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source.

Abstract: Disclosed are methods and systems for etching dielectric layers in a high density plasma etcher. A method includes providing a wafer having a photoresist mask over a dielectric layer in order to define at least one contact via hole or open area that is electrically interconnected down to the silicon substrate of the wafer. The method then proceeds to inserting the wafer into the high density plasma etcher and pulsed application a TCP power source of the high density plasma etcher. The pulsed application includes ascertaining a desired etch performance characteristic, which includes photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source. Then, selecting a duty cycle of the pulsed application of the TCP source and scaling a peak power of the pulsed application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source.