Patents by Inventor Helena Calendar

Helena Calendar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Programmable latches that include non-volatile programmable elements
    Patent number: 6266290
    Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: July 24, 2001
    Assignee: Mosel Vitelic, Inc.
    Inventors: Nikolas Sredanovic, Helena Calendar
  • Programmable latches that include non-volatile programmable elements
    Patent number: 6240034
    Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: May 29, 2001
    Assignee: Mosel Vitelic, Inc.
    Inventors: Nikolas Sredanovic, Helena Calendar
  • Programmable latches that include non-volatile programmable elements
    Patent number: 6222776
    Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.
    Type: Grant
    Filed: September 25, 2000
    Date of Patent: April 24, 2001
    Assignee: Mosel Vitelic, Inc.
    Inventors: Nikolas Sredanovic, Helena Calendar
  • Programmable latches that include non-volatile programmable elements
    Patent number: 6163492
    Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: December 19, 2000
    Assignee: Mosel Vitelic, Inc.
    Inventors: Nikolas Sredanovic, Helena Calendar
  • Initialization of non-volatile programmable latches in circuits in which an initialization operation is performed
    Patent number: 6084803
    Abstract: A non-volatile programmable latch (110) in an integrated circuit (310) is initialized by an initialization signal (SET). At least a portion of the initialization signal is generated in response to a command to the circuit to perform a circuit initialization operation. In some embodiments, the circuit is a synchronous dynamic random access memory (SDRAM), or a synchronous graphics random access memory (SGRAM). The command is a mode register set command (MRS). The command is received when a predetermined period of time has elapsed after power was turned on. Waiting for the predetermined period of time before initializing the latch allows the voltage powering the latch to develop so that the latch can be initialized reliably.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: July 4, 2000
    Assignee: Mosel Vitelic, Inc.
    Inventors: Nikolas Sredanovic, Helena Calendar