Abstract: In an embodiment, a voltage converter includes: a first transistor coupled between a first rail configured to receive a supply voltage and a first node; and an inductance coupled between the first node and a second node configured to deliver an output voltage, wherein, at each operating cycle of the converter, the first transistor is maintained in the on state for a first time period proportional to the inverse of a voltage difference between the supply voltage and the output voltage.

Abstract: In an embodiment, a voltage converter includes: a first transistor coupled between an internal node and a first node receiving a supply voltage; a second transistor coupled between the internal node and a second node receiving a reference voltage; an inductance coupled between the internal node and an output node; a first circuit controlling the first and second transistors; and a second circuit configured to detect, when the first and second transistors are in the off state, when the voltage of the internal node is equal to the voltage of the output node, to condition a switching to the on state of the first transistor.

Abstract: A method for increasing performance of a voltage-buck switched-mode voltage regulator includes generating a first pulse-width modulation signal based on a clock signal, decreasing a frequency of the clock signal to form a modified clock signal, passing the modified clock signal to a digital modulation circuit as a regulated clock signal; and generating a second pulse-width modulation signal based on the regulated clock signal using the digital modulation circuit. The first pulse-width modulation signal includes a period T1 and an off duration D2 corresponding to a first duty cycle. The off duration D2 is an intrinsic pulse-width modulation signal generation latency. The second pulse-width modulation signal includes a period T2 and the off duration D2. The decreased frequency of the modified clock signal causes T2 to be greater than T1 such that a second duty cycle of the second pulse-width modulation signal is increased relative to the first duty cycle.

Abstract: In an embodiment, a voltage comparator includes: a first switch having a conduction terminal coupled to an internal node that is coupled to an output of the voltage comparator; a current source; a capacitor; and a second switch connected in parallel with the capacitor, wherein the current source, the capacitor, and the first switch are coupled in series.

Abstract: The present disclosure relates to a switched-mode Power Supply Buck Converter comprising: a switch connected between a node receiving a supply potential and an internal node; another switch connected between the internal node and a node receiving a reference potential; an inductive element coupling the internal node to an output node; and a control circuit controlling the switches so that current pulses in the inductive element have a maximum value selected from among at least a first value and a second value based on an average current drawn at the output node.

Abstract: In an embodiment, A device includes an operational amplifier and a feedback loop. The feedback loop is coupled between a first input of the operational amplifier and an output of the operational amplifier. The feedback loop is controllable according to a saturation of the operational amplifier. In one example, the device is incorporated in a microcontroller.

Abstract: A method for increasing performance of a voltage-buck switched-mode voltage regulator includes generating a first pulse-width modulation signal based on a clock signal, decreasing a frequency of the clock signal to form a modified clock signal, passing the modified clock signal to a digital modulation circuit as a regulated clock signal; and generating a second pulse-width modulation signal based on the regulated clock signal using the digital modulation circuit. The first pulse-width modulation signal includes a period T1 and an off duration D2 corresponding to a first duty cycle. The off duration D2 is an intrinsic pulse-width modulation signal generation latency. The second pulse-width modulation signal includes a period T2 and the off duration D2. The decreased frequency of the modified clock signal causes T2 to be greater than T1 such that a second duty cycle of the second pulse-width modulation signal is increased relative to the first duty cycle.

Abstract: A method can be used for regulating a pulse-width modulation signal that is driving a voltage-buck switched-mode voltage regulator. The method includes comparing an input voltage of the switched-mode voltage regulator with a threshold voltage. The frequency of the pulse-width modulation signal is decreased when the input voltage is lower than the threshold voltage. The frequency is not decreased when the input voltage is not lower than the threshold voltage.

Abstract: In an embodiment, a voltage converter includes: a first transistor coupled between an internal node and a first node receiving a supply voltage; a second transistor coupled between the internal node and a second node receiving a reference voltage; an inductance coupled between the internal node and an output node; a first circuit controlling the first and second transistors; and a second circuit configured to detect, when the first and second transistors are in the off state, when the voltage of the internal node is equal to the voltage of the output node, to condition a switching to the on state of the first transistor.

Abstract: In an embodiment, a voltage converter includes: a first transistor coupled between a first rail configured to receive a supply voltage and a first node; and an inductance coupled between the first node and a second node configured to deliver an output voltage, wherein, at each operating cycle of the converter, the first transistor is maintained in the on state for a first time period proportional to the inverse of a voltage difference between the supply voltage and the output voltage.

Abstract: In an embodiment, a voltage comparator includes: a first switch having a conduction terminal coupled to an internal node that is coupled to an output of the voltage comparator; a current source; a capacitor; and a second switch connected in parallel with the capacitor, wherein the current source, the capacitor, and the first switch are coupled in series.

Abstract: In an embodiment, A device includes an operational amplifier and a feedback loop. The feedback loop is coupled between a first input of the operational amplifier and an output of the operational amplifier. The feedback loop is controllable according to a saturation of the operational amplifier. In one example, the device is incorporated in a microcontroller.

Abstract: A method can be used for regulating a pulse-width modulation signal that is driving a voltage-buck switched-mode voltage regulator. The method includes comparing an input voltage of the switched-mode voltage regulator with a threshold voltage. The frequency of the pulse-width modulation signal is decreased when the input voltage is lower than the threshold voltage. The frequency is not decreased when the input voltage is not lower than the threshold voltage.

Abstract: An amplifier comprises: first and second supply terminals intended to receive a DC supply voltage; a first branch coupled between the first and second supply terminals and including a first terminal of application of a differential signal to be amplified; a second branch coupled between the first and second supply terminals and including a second terminal of application of the differential signal to be amplified; a third branch coupled between the first and second supply terminals and including a first amplifier having an input terminal connected to the second branch and having an output terminal configured to be coupled to a load, and a measurement element configured to measure a current in the third branch; and a fourth branch coupled between the first and second supply terminals and including a second amplifier having an input terminal connected to the first branch, and a copying element configured to copy the current measured in the third branch.

Abstract: An amplifier comprises: first and second supply terminals intended to receive a DC supply voltage; a first branch coupled between the first and second supply terminals and including a first terminal of application of a differential signal to be amplified; a second branch coupled between the first and second supply terminals and including a second terminal of application of the differential signal to be amplified; a third branch coupled between the first and second supply terminals and including a first amplifier having an input terminal connected to the second branch and having an output terminal configured to be coupled to a load, and a measurement element configured to measure a current in the third branch; and a fourth branch coupled between the first and second supply terminals and including a second amplifier having an input terminal connected to the first branch, and a copying element configured to copy the current measured in the third branch.

Abstract: The data storage device includes several registers that can be addressed by address words, and connected to p output ports through connections that can be configured in response to address words of p registers selected to read the contents of these registers on the p ports respectively. All register address words contain a specific bit with a predetermined rank identical for all address words and remaining bits. The registers are connected in pairs on each output port, each pair of registers containing two registers with address words that only differ in the value of the said specific bit.

Abstract: The data storage device includes several registers that can be addressed by address words, and connected to p output ports through connections that can be configured in response to address words of p registers selected to read the contents of these registers on the p ports respectively. All register address words contain a specific bit with a predetermined rank identical for all address words and remaining bits. The registers are connected in pairs on each output port, each pair of registers containing two registers with address words that only differ in the value of the said specific bit.