Abstract: The present invention discloses a row address decoding system and method for tolerating failures on a pair of wordlines in a memory bank by separately addressing the pair of defective wordlines and replacing the defective wordlines with redundant wordlines in a redundancy block associated with the memory bank. The system of the invention includes a first decoder for decoding the row address signal to generate a first signal addressing wordlines in a first half of the memory bank, and a second decoder for decoding the row address signal with fuse data corresponding to status of fuses associated with wordlines in the memory bank to generate a second signal addressing wordlines in a second half of the memory bank, wherein the first and second signals respectively select first and second wordlines at the same time, and the first and second wordlines are in the first half and the second half of the memory bank, respectively.