Patents by Inventor Helge Simonsen

Helge Simonsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Snoop filter device
    Patent number: 11755485
    Abstract: The invention relates to a device for use in maintaining cache coherence in a multiprocessor computing system. The snoop filter device is connectable with a plurality of cache elements, where each cache element comprises a number of cache agents. The snoop filter device comprises a plurality of snoop filter storage locations, where each snoop filter storage location is mapped to one cache element.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: September 12, 2023
    Assignee: NUMASCALE AS
    Inventors: Thibaut Palfer-Sollier, Steffen Persvold, Helge Simonsen, Mario Lodde, Thomas Moen, Kai Arne Midjås, Einar Rustad, Goutam Debnath
  • Snoop filter device
    Publication number: 20220156195
    Abstract: The invention relates to a device for use in maintaining cache coherence in a multiprocessor computing system. The snoop filter device is connectable with a plurality of cache elements, where each cache element comprises a number of cache agents. The snoop filter device comprises a plurality of snoop filter storage locations, where each snoop filter storage location is mapped to one cache element.
    Type: Application
    Filed: March 13, 2020
    Publication date: May 19, 2022
    Inventors: Thibaut PALFER-SOLLIER, Steffen PERSVOLD, Helge SIMONSEN, Mario LODDE, Thomas MOEN, Kai Arne MIDJÅS, Einar RUSTAD, Goutam DEBNATH
  • Programmable cache coherent node controller
    Patent number: 11157405
    Abstract: A computer system includes a first group of CPU modules operatively coupled to at least one first Programmable ASIC Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second Programmable ASIC Node Controller connected to a second group of CPU modules running a single instance of an operating system.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: October 26, 2021
    Assignee: NUMASCALE AS
    Inventors: Einar Rustad, Helge Simonsen, Steffen Persvold, Goutam Debnath, Thomas Moen
  • Cache coherent node controller for scale-up shared memory systems having interconnect switch between a group of CPUS and FPGA node controller
    Patent number: 10956329
    Abstract: The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 23, 2021
    Assignee: Numascale AS
    Inventors: Einar Rustad, Helge Simonsen, Steffen Persvold, Goutam Debnath, Thomas Moen
  • CACHE COHERENT NODE CONTROLLER FOR SCALE-UP SHARED MEMORY SYSTEMS
    Publication number: 20200089612
    Abstract: The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.
    Type: Application
    Filed: April 30, 2018
    Publication date: March 19, 2020
    Applicant: Numascale AS
    Inventors: Einar Rustad, Helge Simonsen, Steffen Persvold, Goutam Debnath, Thomas Moen
  • PROGRAMMABLE CACHE COHERENT NODE CONTROLLER
    Publication number: 20200050547
    Abstract: A computer system includes a first group of CPU modules operatively coupled to at least one first Programmable ASIC Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second Programmable ASIC Node Controller connected to a second group of CPU modules running a single instance of an operating system.
    Type: Application
    Filed: October 16, 2017
    Publication date: February 13, 2020
    Inventors: Einar RUSTAD, Helge SIMONSEN, Steffen PERSVOLD, Goutam DEBNATH, Thomas MOEN
  • Computer network controller
    Patent number: 6856619
    Abstract: A computer network controller, preferably operative in a System Area Network (SAN), is described. In a SAN, such a network controller is implemented as a SAN Protocol Engine (SPE) for use in Host Channel Adapters (HCA) and Target Channel Adapters (TCA). The SPE is based on a programmable Multi-Context Micro Sequencer (MCMS) tightly coupled to a fully associative multi-context block (FACB), running dedicated instructions optimized for network protocols. Associated with the MCMS is a Data Buffer with a number of read and write ports. This enables the SPE to run different tasks in parallel. Attached to the MCMS is a link-dependent Packet Sender and Outbound Scheduler hereby called Network Protocol Engine (NPE). The SPE is capable of running multiple user-level RMDAs with implicit completion control.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: February 15, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Paal Haugseth, Helge Simonsen