Patents by Inventor Helin Zhang

Helin Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230073224
    Abstract: Methods for initializing a qubit into a pure state, reading the qubit, and arbitrarily rotating the qubit into any quantum state complete in times shorter than the qubit's typical dephasing and relaxation times. These methods provide universal single-qubit control and may be used to implement quantum gates with high fidelity. The methods may be implemented with superconducting qubits, such as heavy fluxonium, and do not rely on a three-dimensional cavity for suppressing spontaneous emission. Therefore, the methods may be implemented using smaller two-dimensional architectures commonly used for superconducting circuits. The methods also work with low-frequency qubits, i.e., qubits for which the energy spacing between the two quantum-computational states is less than the mean thermal energy of a surrounding bath. This reduces the cooling requirements of the qubit while maintaining fidelity.
    Type: Application
    Filed: February 17, 2021
    Publication date: March 9, 2023
    Inventors: David I. Schuster, Helin Zhang
  • Patent number: 11232056
    Abstract: There is disclosed in an example, an endpoint apparatus for an interconnect, comprising: a mechanical and electrical interface to the interconnect; and one or more logic elements comprising an interface vector engine to: receive a first scalar transaction for the interface; determine that the first scalar transaction meets a criterion for vectorization; receive a second scalar transaction for the interface; determine that the second transaction meets the criterion for vectorization; vectorize the first scalar transaction and second scalar transaction into a vector transaction; and send the vector transaction via the electrical interface.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Wenqian Yu, Cunming Liang, Ping Yu, Shun Hao, Helin Zhang
  • Publication number: 20200301861
    Abstract: There is disclosed in an example, an endpoint apparatus for an interconnect, comprising: a mechanical and electrical interface to the interconnect; and one or more logic elements comprising an interface vector engine to: receive a first scalar transaction for the interface; determine that the first scalar transaction meets a criterion for vectorization; receive a second scalar transaction for the interface; determine that the second transaction meets the criterion for vectorization; vectorize the first scalar transaction and second scalar transaction into a vector transaction; and send the vector transaction via the electrical interface
    Type: Application
    Filed: December 28, 2016
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Wenqian Yu, Cunming Liang, Ping Yu, Shun Hao, Helin Zhang