Patents by Inventor Hellen Cheng

Hellen Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power-on solution to avoid crowbar current for multiple power supplies' inputs/outputs
    Patent number: 7233178
    Abstract: Techniques to avoid crowbar current are provided. An integrated circuit according to an embodiment of the present invention includes a first node having a first supply voltage level. A first level shift circuit is connected between the first node and a first path. A second level shift circuit is connected between the first node and a second path. The first path includes an even number of inverter stages, while the second path includes an odd number of inverter stages. The first and second level shift circuits are configured to output a signal at the second supply voltage level. The integrated circuit also includes a PMOS transistor and an NMOS transistor connected in series between a second node having the second supply voltage level and a reference voltage. A gate of the PMOS transistor is connected to the first path, and a gate of the NMOS transistor connected to the second path.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: June 19, 2007
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Talee Yu, Hellen Cheng
  • Power-on solution to avoid crowbar current for multiple power supplies' inputs/outputs
    Publication number: 20060220706
    Abstract: Techniques to avoid crowbar current are provided. An integrated circuit according to an embodiment of the present invention includes a first node having a first supply voltage level. A first level shift circuit is connected between the first node and a first path. A second level shift circuit is connected between the first node and a second path. The first path includes an even number of inverter stages, while the second path includes an odd number of inverter stages. The first and second level shift circuits are configured to output a signal at the second supply voltage level. The integrated circuit also includes a PMOS transistor and an NMOS transistor connected in series between a second node having the second supply voltage level and a reference voltage. A gate of the PMOS transistor is connected to the first path, and a gate of the NMOS transistor connected to the second path.
    Type: Application
    Filed: April 19, 2005
    Publication date: October 5, 2006
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Talee Yu, Hellen Cheng