Abstract: The invention relates to a method for preventing total failure in a processing unit for sending and receiving protocol information for a large number of transmission channels, wherein a protocol process is started by a controller for every protocol and a separate monitoring process that monitors the orderly time duration of the protocol process can be activated or deactivated parallel thereto for every protocol process. If the previously determined time duration of the protocol process is exceeded, the monitoring process reports it to the controller, whereupon the controller stores relevant data for subsequent localization of errors.

Abstract: The invention relates to a method for preventing total failure in a processing unit for sending and receiving protocol information for a large number of transmission channels, wherein a protocol process is started by a controller for every protocol and a separate monitoring process that monitors the orderly time duration of the protocol process can be activated or deactivated parallel thereto for every protocol process. If the previously determined time duration of the protocol process is exceeded, the monitoring process reports it to the controller, whereupon the controller stores relevant data for subsequent localization of errors.

Abstract: The units (CTR0, CTR1) are controlled by mutually independent clock pulses (SCLK, RXCK). In order to prevent the loss of microsynchronization when information is transferred from one clock system to the other and as a result of different error situations as regards the information received by the units, the information received is temporarily stored before being passed on for processing or the result information is temporarily stored before being transmitted. If reception is error free, the units are cross-synchronized. In the absence of a synchronization signal in one partner unit owing to faulty reception, this unit rejects the information received despite the fact that it is error free.

Abstract: For implementing the method for reading error statistics data, a hardware configuration has processing units (CTR0, CTR1) that operated in microsynchronous parallel operation for the processing of ATM information. The processing units are connected at the ATM end to a switching matrix (SN0, SN1) and via a bus interface (B-I) to a central processor. The central processor is used for evaluating error statistics arising in the processing units and for monitoring the synchronous operation by comparing the processing results. The error statistics data is packed into ATM transmitter cells and looped back via the switching matrix in each case to both processing units and then supplied to the central processor via the bus interface. This prevents the erroneous indication of the loss of microsynchronism when error statistics for the two processing units differ.

Abstract: A switched-capacitor sigma-delta modulator includes at least one memory element, at least one comparator, and at least one integrator. The at least one integrator has an input stage including a series circuit of a first switch, a first capacitor and a second switch, a third switch for connecting one of the two terminals of the first capacitor to ground potential, and a fourth switch for connecting the other of the two terminals of the first capacitor to ground potential. A nodal point is connected between the second and fourth switches and the other of the two terminals of the first capacitor. A negative feedback stage includes second and third capacitors each having one terminal connected to the nodal point. A fifth switch connects the other terminal of the second capacitor to a first potential. A sixth switch connects the other terminal of the third capacitor to a second potential. Seventh and eighth series-connected switches connect the other terminal of the second capacitor to the second potential.