Abstract: The invention relates to a high voltage resistant edge structure in the edge region of a semiconductor component which has floating guard rings of the first conductivity type and inter-ring zones of the second conductivity type which are arranged between the floating guard rings, wherein the conductivities and/or the inter-ring zones are set such that their charge carriers are totally depleted when blocking voltage is applied. The inventive edge structure achieves a modulation of the electrical field both at the surface and in the volume of the semiconductor body. If the inventive edge structure is suitably dimensioned, the field intensity maximum can easily be situated in the depth; that is, in the region of the vertical p-n junction. Thus, a suitable edge construction which permits a “soft” leakage of the electrical field in the volume can always be provided over a wide range of concentrations of p and n doping.

Abstract: A method is provided for fabricating a body region of a first conduction type for a vertical MOS transistor configuration in a semiconductor body such that the body region has a reduced resistivity without a corresponding reduction in the breakdown voltage of the transistor. The method includes, inter alia: performing a first implantation of a doping material of a first conduction type into the semiconductor body such that an implantation maximum of the first implantation lies within the semiconductor body set back from the channel region; and performing a second implantation of a doping material of the first conduction type such that an implantation maximum of the second implantation lies within the semiconductor body below the implantation maximum of the first implantation. The dose of the second implantation is less than the dose of the first implantation.

Abstract: A method is provided for fabricating a body region of a first conduction type for a vertical MOS transistor configuration in a semiconductor body such that the body region has a reduced resistivity without a corresponding reduction in the breakdown voltage of the transistor. The method includes, inter alia: performing a first implantation of a doping material of a first conduction type into the semiconductor body such that an implantation maximum of the first implantation lies within the semiconductor body set back from the channel region; and performing a second implantation of a doping material of the first conduction type such that an implantation maximum of the second implantation lies within the semiconductor body below the implantation maximum of the first implantation. The dose of the second implantation is less than the dose of the first implantation.

Abstract: The power switch has considerably reduced common-mode interference and relatively reduced circuit complexity. The power switch is formed of a semiconductor chip on a leadframe. A first terminal of the semiconductor chip is connected to the active potential and a second terminal for inactive potential is connected to the leadframe. The second terminal is either the drain of a transistor or the anode of a diode.

Abstract: A method for fabricating field effect-controlled semiconductor components, such as e.g. but not exclusively MIS power transistors. The field effect-controllable semiconductor component has a semiconductor substrate of a first conductivity type and a gate insulator layer on the surface of the semiconductor substrate. A well of a second conductivity type is produced in the semiconductor substrate by implanting first impurity atoms. A semiconductor layer having a first predetermined thickness is produced on the gate insulator layer prior to the production of the well. The semiconductor layer is reduced in a predtdermined region to obtain a residual layer having a second predetermined thickness, such that the semiconductor layer acts as an implantation barrier outside the predetermined region when the well is produced.

Abstract: A semiconductor component having a high-voltage endurance edge structure in which a multiplicity of parallel-connected individual components are disposed in a multiplicity of cells of a cell array. In an edge region, the semiconductor component has cells with shaded source zone regions. During commutation of the power semiconductor component, the shaded source zone regions suppress the switching on of a parasitic bipolar transistor caused by the disproportionately large reverse flow current density. Moreover, an edge structure having shaded source zone regions can be produced very easily in technological terms, in particular in the case of self-adjusting processes, and can thus be produced cost-effectively.