Abstract: A method of forming a buried collar on the sidewall of a trench in a semiconductor substrate including: (a) providing the trench in the semiconductor substrate, the trench having a first dielectric layer formed on a sidewall in a upper region of the trench and a conductive material filling a lower region of the trench, the conductive material covering a lower portion of the first dielectric layer; (b) removing the first dielectric layer not covered by the conductive material; (c) forming a second dielectric layer on the exposed sidewall of the upper region and on a top surface of the conductive material; (d) removing an uppermost portion of the second dielectric layer from the sidewall in the upper region; (e) forming a third dielectric layer on the exposed sidewall of the upper region; and (f) increasing the thickness of the second dielectric layer to form the buried collar.

Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

Abstract: A process as shown in FIGS. 1A through 1I, or FIGS. 2A through 2I for providing first areas of gate oxide (30, 30A, 30B) on a substrate (10) having a first thickness and second adjacent areas (32, 32A, 32B) of gate oxide having a lesser thickness without the use of a N2 implantation process.

Abstract: A process for forming an oxide layer on a sidewall of a trench in a substrate. The process comprises the steps of forming the trench in the substrate, forming a nitride interface layer over a portion of the trench sidewall, forming an amorphous layer over the nitride interface layer, and oxidizing the amorphous layer to form the oxide layer. The process may be used, for example, to form a gate oxide for a vertical transistor, or an isolation collar. The invention also comprises a semiconductor memory device comprising a substrate, a trench in the substrate having a sidewall, an isolation collar comprising an isolation collar oxide layer on the trench sidewall in an upper region of the trench, and a vertical gate oxide comprising a gate oxide layer located on the trench sidewall above the isolation collar.

Abstract: A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a <100> crystal plane and a <110> crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the <110> crystal plane of the trench side wall, but not into the <100> crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.

Abstract: A process for fabricating a gate oxide of a vertical transistor. In a first step, a trench is formed in a substrate, the trench extending from a top surface of the substrate and having a trench bottom and a trench side wall. The trench side wall comprises a <100> crystal plane and a <110> crystal plane. Next, a sacrificial layer having a uniform thickness is formed on the trench side wall. Following formation of the sacrificial layer, nitrogen ions are implanted through the sacrificial layer such that the nitrogen ions are implanted into the <110> crystal plane of the trench side wall, but not into the <100> crystal plane of the trench side wall. The sacrificial layer is then removed and the trench side wall is oxidized to form the gate oxide.