Abstract: To allow a simple cascading without any optical crosstalk at the connection points, an optoelectronic sensor is provided having at least one electronic card which has light transmitter elements and/or light reception elements and having at least two optical modules which can be fastened to the electronic card, wherein each optical module comprises a tube array, which has a plurality of tubes, an open end and a closed end, wherein the open end of the optical module comprises an open first connection element of a connection to the tube array and comprises wall connection elements and wherein the closed end of the optical module comprises a closed second connection element of the connection which has an outer wall which is formed with shape matching to the wall connection elements of the open end of the optical module such that, on a plugging together of an open end of an optical module and of a closed end of a further optical module, the two connection elements of the connection form a connection tube which is

Abstract: To allow a simple cascading without any optical crosstalk at the connection points, an optoelectronic sensor is provided having at least one electronic card which has light transmitter elements and/or light reception elements and having at least two optical modules which can be fastened to the electronic card, wherein each optical module comprises a tube array, which has a plurality of tubes, an open end and a closed end, wherein the open end of the optical module comprises an open first connection element of a connection to the tube array and comprises wall connection elements and wherein the closed end of the optical module comprises a closed second connection element of the connection which has an outer wall which is formed with shape matching to the wall connection elements of the open end of the optical module such that, on a plugging together of an open end of an optical module and of a closed end of a further optical module, the two connection elements of the connection form a connection tube which is

Abstract: Clocking scheme to clock a monolithic integrated circuit, having a basic clock rate (c0) generated by a clock source which is coupled to N intermediate clocks (c1 through cN) which are delayed relative to each other, wherein the individual delays (t) are distributed within a period T of the basic lock rate. Each of the N intermediate clocks (c1 through cN) supplies at least one of M data-processing blocks (D1 through DM). To effect a transfer of data between a transmitting data-processing block (D2) and a receiving data-processing block (D1), the delay of the intermediate clock assigned to the intermediate clock (c2) is greater than the delay of the intermediate clock (c1) assigned to the receiving data-processing block.

Abstract: Clocking scheme to clock a monolithic integrated circuit, having a basic clock rate (c0) generated by a clock source which is coupled to N intermediate clocks (c1 through cN) which are delayed relative to each other, wherein the individual delays (t) are distributed within a period T of the basic clock rate. Each of the N intermediate clocks (c1 through cN) supplies at least one of M data-processing blocks (D1 through DM). To effect a transfer of data between a transmitting data-processing block (D2) and a receiving data-processing block (D1), the delay of the intermediate clock assigned to the intermediate clock (c2) is greater than the delay of the intermediate clock (c1) assigned to the receiving data-processing block.