Patents by Inventor Helmut Kandolf

Helmut Kandolf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7362650
    Abstract: Embodiments of the invention provide a memory arrangement having an even number k=4 of physically spaced RAM chips, on each of which it is possible for m data items to be simultaneously written or read via an m-bit data bus, also having a register for buffer-storing and transmitting n respective parallel data bits as a packet between an n-bit parallel port and the data buses, and having a selection device which responds to selection bits in order to select a respective separate cell group within the plurality of the chips for each of the disjoint m-bit groups (d) of the n-bit packet. The k chips are classified into q=2 disjoint chip groups, each of which comprises k/q chips which differ as little as possible from one another in terms of their distance from the register. The number m is chosen to be equal to q*n/k, and the selection device is designed to select a respective separate chip from the same chip group and a cell group in this chip for each m-bit group of the same n-bit packet.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: April 22, 2008
    Assignee: Infineon Technologies AG
    Inventors: Helmut Kandolf, Sven Kalms, Maksim Kuzmenka, Michael Hausmann
  • Patent number: 7191276
    Abstract: One embodiment of the invention provides a hub chip comprising: an address bus input for receiving a plurality of successively sent portions of address and/or command data, a shift register which has register elements and is connected to the address bus input to receive the plurality of portions of the address and/or command data, the shift register being connected to the address bus input so that, when the address and/or command data are received, the portions of the address and/or command data are successively written to the register elements, an address bus output for outputting the received address and/or command data, a memory module interface for connecting one or more memory modules, where the hub chip addresses none, one or a plurality of the connected memory modules, depending on the address and/or command data transferred, and a driver element provided to output the received portion of the address and/or command data to the address bus output before all of the portions of the address and/or command
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: March 13, 2007
    Assignee: Infineon Technologies AG
    Inventors: Sven Kalms, Helmut Kandolf
  • Publication number: 20060250881
    Abstract: Embodiments of the invention provide a memory arrangement having an even number k=4 of physically spaced RAM chips, on each of which it is possible for m data items to be simultaneously written or read via an m-bit data bus, also having a register for buffer-storing and transmitting n respective parallel data bits as a packet between an n-bit parallel port and the data buses, and having a selection device which responds to selection bits in order to select a respective separate cell group within the plurality of the chips for each of the disjoint m-bit groups (d) of the n-bit packet. The k chips are classified into q=2 disjoint chip groups, each of which comprises k/q chips which differ as little as possible from one another in terms of their distance from the register. The number m is chosen to be equal to q*n/k, and the selection device is designed to select a respective separate chip from the same chip group and a cell group in this chip for each m-bit group of the same n-bit packet.
    Type: Application
    Filed: March 30, 2006
    Publication date: November 9, 2006
    Inventors: Helmut Kandolf, Sven Kalms, Maksim Kuzmenka, Michael Hausmann
  • Publication number: 20050027923
    Abstract: One embodiment of the invention provides a hub chip comprising: an address bus input for receiving a plurality of successively sent portions of address and/or command data, a shift register which has register elements and is connected to the address bus input to receive the plurality of portions of the address and/or command data, the shift register being connected to the address bus input so that, when the address and/or command data are received, the portions of the address and/or command data are successively written to the register elements, an address bus output for outputting the received address and/or command data, a memory module interface for connecting one or more memory modules, where the hub chip addresses none, one or a plurality of the connected memory modules, depending on the address and/or command data transferred, and a driver element provided to output the received portion of the address and/or command data to the address bus output before all of the portions of the address and/or command
    Type: Application
    Filed: June 25, 2004
    Publication date: February 3, 2005
    Inventors: Sven Kalms, Helmut Kandolf
  • Patent number: 6816406
    Abstract: A magnetic memory configuration stores data and avoids ageing effects. The memory configuration contains a cell array containing magnetic memory cells disposed along a first direction and a second direction crossing the former, a multiplicity of electrical lines along the first direction, and a multiplicity of electrical lines along the second direction. The magnetic memory cells in each case are disposed at crossover points of the electrical lines. A first current supply device supplies respectively selected electrical lines along the first direction with current. A second current supply device supplies respectively selected electrical lines along the second direction with current. The second current supply device is configured for setting the direction of the current in accordance with an information item to be written. The first current supply device is suitable for changing over the direction of the current as desired.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: November 9, 2004
    Assignee: Infineon Technologies AG
    Inventors: Heinz Hönigschmid, Helmut Kandolf, Stefan Lammers
  • Patent number: 6759874
    Abstract: An electronic circuit has a driver circuit to drive a signal onto a signal line. The driver circuit contains a first switching device with a first forward resistance between a first supply voltage terminal and the signal line, and a second switching device with a second forward resistance between a second supply voltage terminal and the signal line. A control circuit is provided to generate a first and a second control signal to control the first and second switching devices in a first operating mode such that, depending on the signal which is to be driven, either the first switching device or the second switching device is through-connected. In a second operating mode, the first switching device and the second switching device are essentially through-connected with the aid of the first and second control signals so that the first and second forward resistances together form a terminating resistance.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: July 6, 2004
    Assignee: Infineon Technologies AG
    Inventors: Georg Braun, Helmut Kandolf
  • Publication number: 20040100836
    Abstract: A magnetic memory configuration stores data and avoids ageing effects. The memory configuration contains a cell array containing magnetic memory cells disposed along a first direction and a second direction crossing the former, a multiplicity of electrical lines along the first direction, and a multiplicity of electrical lines along the second direction. The magnetic memory cells in each case are disposed at crossover points of the electrical lines. A first current supply device supplies respectively selected electrical lines along the first direction with current. A second current supply device supplies respectively selected electrical lines along the second direction with current. The second current supply device is configured for setting the direction of the current in accordance with an information item to be written. The first current supply device is suitable for changing over the direction of the current as desired.
    Type: Application
    Filed: November 17, 2003
    Publication date: May 27, 2004
    Inventors: Heinz Honigschmid, Helmut Kandolf, Stefan Lammers
  • Patent number: 6657916
    Abstract: An integrated memory has a memory cell array with memory cells which are connected to word lines and bit lines. For the purpose of reading from or writing to one of the memory cells, a first word line can be connected to a supply circuit via a controllable first switching device and a second word line can be connected to the supply circuit via a controllable second switching device. A control circuit can drive the first switching device in dependence of an activation state of the second word line and the second switching device in dependence of an activation state of the first word line. Consequently, existing word lines that are not currently being used can be used for addressing one of the memory cells. As a result, only one wiring plane is required for the word lines.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: December 2, 2003
    Assignee: Infineon Technologies AG
    Inventors: Heinz Hönigschmid, Stefan Lammers, Helmut Kandolf
  • Patent number: 6639829
    Abstract: A configuration and method for low-loss writing of an MRAM includes setting voltages at bit lines and word lines such that the voltage across the memory cells between a selected word/bit line and the individual bit line/word lines is minimal. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the memory cell and voltages at the bit/word lines are set to minimize a cell voltage across the memory cells between a selected word/bit line and individual bit/word lines. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the particular cell, and, when a voltage V1 and a voltage V2<V1 are present at a respective end of the selected word line/bit lines, the cell field is configured to have all of the bit/word lines set to voltages (V1+V2)/2 and to have a maximum cell voltage of ±(V1−V2)/2.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: October 28, 2003
    Assignee: Infineon Technologies AG
    Inventors: Dietmar Gogl, Helmut Kandolf, Stefan Lammers
  • Patent number: 6618306
    Abstract: A digital circuit configuration includes a memory matrix having M rows and N columns and P<M additional rows and Q<N additional columns, and an addressing device whose address connection contacts are sufficient precisely for addressing the M rows and N columns. To address the additional rows and columns as well, particularly, for test purposes, only a single control bit connection contact is provided with a changeover device responding to control bits from the control bit connection contact and from dedicated address connection contacts to associate applied address bits either with addressing of the M rows and N columns or the additional rows and columns. The numbers P and Q are chosen such that the addressing of P elements requires at least two bits fewer than the addressing of M elements, and such that the addressing of Q elements requires at least two bits fewer than the addressing of N elements.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: September 9, 2003
    Assignee: Infineon Technologies AG
    Inventors: Thomas Böhm, Helmut Kandolf, Stefan Lammers, Zoltan Manyoki
  • Patent number: 6577528
    Abstract: A circuit configuration for controlling write operations and read operations in an MRAM memory configuration includes selection transistors grouped in sections of equal numbers of the selection transistors. The selection transistors of each of the sections are jointly connected, at the ends of the bit lines, to a respective interacting pair of read/write amplifiers via those electrode terminals of the selection transistors that are not connected to the bit lines. The read/write amplifiers are controlled such that if a write signal is fed thereto, write currents for writing a logic “1” or “0” flow in a first direction or a second direction in all of the bit lines selected by a corresponding column select signal and, if a read signal is fed in, a logic state stored in one of the magnetoresistive memory cells can be read out.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: June 10, 2003
    Assignee: Infineon Technologies AG
    Inventors: Dietmar Gogl, Helmut Kandolf, Heinz Hönigschmid
  • Publication number: 20030057994
    Abstract: An electronic circuit has a driver circuit to drive a signal onto a signal line. The driver circuit contains a first switching device with a first forward resistance between a first supply voltage terminal and the signal line, and a second switching device with a second forward resistance between a second supply voltage terminal and the signal line. A control circuit is provided to generate a first and a second control signal to control the first and second switching devices in a first operating mode such that, depending on the signal which is to be driven, either the first switching device or the second switching device is through-connected. In a second operating mode, the first switching device and the second switching device are essentially through-connected with the aid of the first and second control signals so that the first and second forward resistances together form a terminating resistance.
    Type: Application
    Filed: September 23, 2002
    Publication date: March 27, 2003
    Inventors: Georg Braun, Helmut Kandolf
  • Publication number: 20030039157
    Abstract: A digital circuit configuration includes a memory matrix having M rows and N columns and P<M additional rows and Q<N additional columns, and an addressing device whose address connection contacts are sufficient precisely for addressing the M rows and N columns. To address the additional rows and columns as well, particularly, for test purposes, only a single control bit connection contact is provided with a changeover device responding to control bits from the control bit connection contact and from dedicated address connection contacts to associate applied address bits either with addressing of the M rows and N columns or the additional rows and columns. The numbers P and Q are chosen such that the addressing of P elements requires at least two bits fewer than the addressing of M elements, and such that the addressing of Q elements requires at least two bits fewer than the addressing of N elements.
    Type: Application
    Filed: September 9, 2002
    Publication date: February 27, 2003
    Inventors: Thomas Bohm, Helmut Kandolf, Stefan Lammers, Zoltan Manyoki
  • Patent number: 6515890
    Abstract: An integrated semiconductor memory has memory cells with a ferroelectric memory property. The memory cells are in each case connected between a column line and a charge line. The column line is connected to a read amplifier which supplies an output signal. The charge line is connected to a driver circuit which provides the charge line with a given potential. In an inactive mode, the column line and the charge line are jointly connected to a connection for a common supply potential in the read amplifier or in the driver circuit. As a result, a relatively quick equalization of a potential between the lines is possible. Thus, unintended changes in the memory cell content due to interfering voltages are avoided.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: February 4, 2003
    Assignee: Infineon Technologies AG
    Inventors: Robert Esterl, Helmut Kandolf, Heinz Hönigschmid, Thomas Röhr
  • Patent number: 6473335
    Abstract: A magneto-resistive random access memory (MRAM) configuration is described in which line driver circuits are respectively assigned via connecting nodes to two memory cell arrays, with the result that the area for the driver circuits can practically be halved. Therefore a space-saving architecture and a more efficient MRAM configuration is obtained.
    Type: Grant
    Filed: July 3, 2001
    Date of Patent: October 29, 2002
    Assignee: Infineon Technologies AG
    Inventors: Thomas Böhm, Helmut Kandolf, Stefan Lammers
  • Patent number: 6459631
    Abstract: The invention relates to a configuration for implementing redundancy for a memory chip, in which a fuse bank is connected to a comparator via a redundancy predecoder so that predecoded addresses can be compared with one another in the comparator and undecoded addresses can be stored in the fuse bank. This provides for a low-power and space-saving design.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: October 1, 2002
    Assignee: Infineon Technologies AG
    Inventors: Helmut Fischer, Helmut Kandolf, Stefan Lammers
  • Patent number: 6445607
    Abstract: A description is given of a method for operating an integrated memory which has memory cells each having a selection transistor and a storage capacitor with a ferroelectric storage effect. The memory contains a plate line, which is connected to one of the column lines via a series circuit containing a selection transistor and a storage capacitor of respective memory cells. A memory access is carried out according to the “pulsed plate concept”. In this case, the temporal sequence is controlled in such a way that, in an access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by the same amount. An attenuation or destruction of the information stored in the memory cells, which is caused by source-drain leakage currents of unactivated selection transistors, is thus avoided.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: September 3, 2002
    Assignee: Infineon Technologies AG
    Inventors: Robert Esterl, Heinz Hönigschmid, Helmut Kandolf, Thomas Röhr
  • Publication number: 20020116591
    Abstract: An integrated memory has a memory cell array with memory cells which are connected to word lines and bit lines. For the purpose of reading from or writing to one of the memory cells, a first word line can be connected to a supply circuit via a controllable first switching device and a second word line can be connected to the supply circuit via a controllable second switching device. A control circuit can drive the first switching device in dependence of an activation state of the second word line and the second switching device in dependence of an activation state of the first word line. Consequently, existing word lines that are not currently being used can be used for addressing one of the memory cells. As a result, only one wiring plane is required for the word lines.
    Type: Application
    Filed: January 22, 2002
    Publication date: August 22, 2002
    Inventors: Heinz Honigschmid, Stefan Lammers, Helmut Kandolf
  • Publication number: 20020080661
    Abstract: A circuit configuration for controlling write operations and read operations in an MRAM memory configuration includes selection transistors grouped in sections of equal numbers of the selection transistors. The selection transistors of each of the sections are jointly connected, at the ends of the bit lines, to a respective interacting pair of read/write amplifiers via those electrode terminals of the selection transistors that are not connected to the bit lines. The read/write amplifiers are controlled such that if a write signal is fed thereto, write currents for writing a logic “1” or “0” flow in a first direction or a second direction in all of the bit lines selected by a corresponding column select signal and, if a read signal is fed in, a logic state stored in one of the magnetoresistive memory cells can be read out.
    Type: Application
    Filed: December 17, 2001
    Publication date: June 27, 2002
    Inventors: Dietmar Gogl, Helmut Kandolf, Heinz Honigschmid
  • Publication number: 20020021543
    Abstract: A configuration and method for low-loss writing of an MRAM includes setting voltages at bit lines and word lines such that the voltage across the memory cells between a selected word/bit line and the individual bit line/word lines is minimal. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the memory cell and voltages at the bit/word lines are set to minimize a cell voltage across the memory cells between a selected word/bit line and individual bit/word lines. A voltage drop occurs on a selected word/bit line connected to a particular memory cell when writing into the particular cell, and, when a voltage V1 and a voltage V2<V1 are present at a respective end of the selected word line/bit lines, the cell field is configured to have all of the bit/word lines set to voltages (V1+V2)/2 and to have a maximum cell voltage of ±(V1-V2)/2.
    Type: Application
    Filed: August 3, 2001
    Publication date: February 21, 2002
    Inventors: Dietmar Gogl, Helmut Kandolf, Stefan Lammers