Abstract: A multiplicity of nanotubes are applied to at least one external chip metal contact of an electronic chip in order to make contact between the electronic chip and a further electronic chip.

Abstract: A semiconductor memory device with a phase transformation memory effect includes at least one memory element in a semiconductor substrate, and a cavity arrangement including at least one cavity in spatial proximity to the respective memory element. The cavity is in spatial arrangement with the respective memory element so as to reduce thermal coupling of the respective memory element to the areas surrounding the memory element, which also reduces the thermal conductivity between memory element and the areas surrounding the memory element.

Abstract: A multiplicity of nanotubes are applied to at least one external chip metal contact of the electronic chip in order to make contact between the electronic chip and a further electronic chip.

Abstract: A rail brake element, in particular in connection with rail brake buffer blocks, comprising a pair of clamping plates C-shaped in cross section and having upper and lower leg portions, the clamping plates engaging a rail head on opposite sides, at least one braking block element having a flat lower surface which engages the top surface of the rail head and two upper roof-like tapered surfaces, whereby the block element and the brake linings are pressed against the rail head, characterized in that the tapered surfaces of the block element have an angle relative to a horizontal plane of at least 20° and the block element and the clamping plates are dimensioned such that the end of the upper leg portions of the clamping plates have a significant distance from the upper edge of the associated tapered surface if the rail head is not worn.

Abstract: A semiconductor memory cell, in accordance with the present invention includes a deep trench formed in a substrate. The deep trench includes a storage node in a lower portion of the deep trench, and a gate conductor formed in an upper portion of the deep trench. The gate conductor is electrically isolated from the storage node. An active area is formed adjacent to the deep trench and is formed in the substrate to provide a channel region of an access transistor of the memory cell. A buried strap is formed to electrically connect the storage node to the active area when the gate conductor is activated. A body contact is formed opposite the deep trench in the active area and corresponding in position to the buried strap to prevent floating body effects due to outdiffusion of the buried strap. Methods for forming the body contact are also described.

Abstract: A memory cell array has memory cells in which there is an electrical connection between a polycrystalline semiconductor material of a capacitor electrode and a monocrystalline semiconductor region. Islands made of an amorphous material are disposed in a vicinity of the electrical connection between the polycrystalline semiconductor material and the monocrystalline semiconductor region. The islands are produced in particular by thermally breaking up an amorphous layer which has been formed by thermal oxidation. The memory cell array is in particular a DRAM array with a trench capacitor.

Abstract: A rail brake element, in particular in connection with rail brake buffer blocks, comprising a pair of clamping plates C-shaped in cross section and having upper and lower leg portions, the clamping plates engaging a rail head on opposite sides, at least one braking block element having a flat lower surface which engages the top surface of the rail head and two upper roof-like tapered surfaces, the upper leg portions of the clamping plates engaging the associated tapered surfaces, the lower leg portions having at the side facing the rail head a brake lining in engagement with the lower surfaces of the rail head, and at least one clamping bolt by which the clamping plates can be pressed towards each other, whereby the block element and the brake linings are pressed against the rail head, characterized in that the tapered surfaces of the block element have an angle relative to a horizontal plane of at least 20° and the block element and the clamping plates are dimensioned such that the end of the upper leg p

Abstract: An integrated circuit configuration, in particular is a DRAM cell configuration, includes a capacitor disposed on a first substrate and a portion with a contact disposed on a second substrate. The first substrate is connected to the second substrate, with the contact adjoining the capacitor. The first substrate and the second substrate can be connected essentially in an unadjusted manner, if capacitor elements are distributed over the first substrate and a contact surface of the contact is so large that when the substrates are connected, the contact in each case adjoins at least one of the capacitor elements, which then defines the capacitor. The capacitor may include a plurality of capacitor elements, which makes its capacitance especially high. A method is also provided for producing the integrated circuit configuration.

Abstract: A semiconductor memory cell, in accordance with the present invention includes a deep trench formed in a substrate. The deep trench includes a storage node in a lower portion of the deep trench, and a gate conductor formed in an upper portion of the deep trench. The gate conductor is electrically isolated from the storage node. An active area is formed adjacent to the deep trench and is formed in the substrate to provide a channel region of an access transistor of the memory cell. A buried strap is formed to electrically connect the storage node to the active area when the gate conductor is activated. A body contact is formed opposite the deep trench in the active area and corresponding in position to the buried strap to prevent floating body effects due to outdiffusion of the buried strap. Methods for forming the body contact are also described.

Abstract: A read-only memory cell device includes a substrate formed of semiconductor material and having a main area. Memory cells in the vicinity of the main area are disposed in matrix form in columns and rows in a cell field. Each memory cell has in each case at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode. The MOS transistors of a column are connected in series one after the other. Each column is connected to a bit line and the gate electrodes of the MOS transistors of a row are connected to a word line. The source and drain regions of the MOS transistors of a column are formed in source/drain webs running substantially parallel to one another at a predetermined spacing, are electrically insulated from one another, are produced from the semiconductor material of the substrate and have a predetermined web depth, starting from the main area of the substrate.

Abstract: An element that prevents the formation of a channel is arranged in a level of the channel region (Kaa) at one of two opposite sidewalls of a semiconductor structure that has a source/drain region (S/D1a) and a channel region (Kaa) of a vertical selection transistor arranged therebelow. The source/drain region as well as a respective word line (W1a) adjoin at both sidewalls. For folded bit lines (B1a), respectively two word lines (W1a) can be formed in the trenches (G2a). The elements of semiconductor structures neighboring along one of the trenches (G2a) are then arranged in alternation at a sidewall of the trench (G2a) and at a sidewall of a neighboring trench (D2a). A storage capacitor can be arranged over a substrate (1a) or can be buried in the substrate (1a). The connection of the selection transistor to a bit line (B1a) can ensue in many ways.

Abstract: A read-only memory cell configuration and a method for its production include a substrate formed of semiconductor material having memory cells disposed in a cell field in a region of a main area. Each memory cell has at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode. The drain region is connected to a bit line and the gate electrode is connected to a word line. The MOS transistor is formed by a trench starting at the main area and reaching as far as the source region. Side walls of the trench are disposed at an angle of approximately 45.degree. to approximately 80.degree. relative to the main area and are doped with a doping material of a predetermined conductivity for defining the programming of the MOS transistor.

Abstract: For manufacturing a capacitor, in particular for a dynamic memory cell arrangement, a trench is etched in a substrate. In the trench, a layer sequence is produced that contains, in alternating fashion, layers of doped silicon and germanium-containing layers. By anisotropic etching, the surface of the semiconductor substrate (12) is exposed in the region of the trench floor. The trenches are filled with a conductive support structure (20). The germanium-containing layers are removed selectively to the layers of doped silicon. The exposed surface of the layers of doped silicon (17) and of the support structure (20) are provided with a capacitor dielectric (22), onto which is applied a counter-electrode (23).

Abstract: A method and apparatus for the reversible contacting of a semiconductor circuit level to assist in performing a function test. The apparatus includes a testing head having test points arranged at a test side lying opposite the contact surfaces of a semiconductor circuit level. The test points are formed of liquid contacts in recesses in the test side of the testing head wherein the liquid contacts form menisci that project beyond the surface of the testing head. The recesses, in turn, are provided for metallizations which are connected to electrically-conductive leads. In addition, the surface may be provided with a roughening or with etched trenches.

Abstract: A terminal metallization (8) is applied onto and structured on a layer structure on the upper side of the component, the terminal metallization is applied on the upper side of an insulating layer (7) with an opening on a metallization (6) provided for electrical connection. By filling a hole produced in a covering dielectric with metal, a contact rod (12) seated on this terminal metallization (8) is formed. This contact rod is resiliently movable in a surrounding opening (14) of the component on the free part of the terminal metallization (8) anchored in the layer structure. This enables the reversible contacting of the component to a further component arranged vertically thereto, whereby the planar upper sides lying opposite one another can be brought into intimate contact because the contact rod (12) pressed against a contact (15) of the other component is pressed back into the opening (14) and an adequately firm connection of the contacts is achieved by the spring power of the terminal metallization (8).

Abstract: A method of manufacturing a semiconductor component, wherein capacitances occurring between contacts, interconnects or metallizations are reduced by filling cavities with air or gas is provided. The cavities are produced between the semiconductor material and a passivation layer in a region wherein the interconnects are surrounded by dielectric and are subsequently closed by a further passivation layer.

Abstract: A component having a movable micro mechanical function element arranged in a cavity having a cover layer supported by webs or pillar-like supports is provided. The movable element is potentially covered with a termination layer for closing the etching holes present in the cover layer. Electrical terminals of the movable part, the cover layer and doped regions produced in the substrate as a cooperating electrode enable the realization of an acceleration sensor that is easy to mount in a housing.

Abstract: A process for producing components having a contact structure provides for vertical contact-making, in which, for the connection of a metal contact of a first component to a metal contact of a second component, the substrate is etched out, starting from the top, in a region provided for a vertical, conductive connection, this recess is filled with a metal so that said metal is connected to the surface of the metal contact, the rear side of the substrate is removed until the metal projects beyond the rear side, a metallization layer made of a metal having a low melting point, for example AuIn, is applied to the metal contact of the second component, the surface of the second component is provided with a planar layer, the two components are arranged vertically with respect to one another and a permanent contact is produced between the metal of the first component and the metallization layer of the second component by pressing one onto the other and heating.

Abstract: A component having a movable micromechanical function element arranged in a cavity having a cover layer supported by webs or pillar-like supports is provided. The movable element is potentially covered with a termination layer for closing the etching holes present in the cover layer. Electrical terminals of the movable part, the cover layer and doped regions produced in the substrate as a cooperating electrode enable the realization of an acceleration sensor that is easy to mount in a housing.

Abstract: To produce a three-dimensional circuit arrangement, a first substrate (1) is thinned, stacked onto a second substrate (2) and fixedly connected to the latter. The first substrate (1) and the second substrate (2) in this case each comprise circuit structures (12, 22) and metallization planes (13, 23). At least one first contact hole (16) and one second contact hole (4) are opened, which reach the metallization plane (13, 23) in the first substrate (1) and second substrate (2), respectively, the second contact hole (4) passing through the first substrate (1). The metallization planes (13, 23) of the two substrates (1, 2) are electrically connected to one another via a conductive layer (7).