Abstract: A circuit arrangement is disclosed for the summation of products formed from analog signals and digital coefficients. A multiplying digital-analog converter is provided having a reference input for receiving analog signals at successive points in time. A data input of the digital-analog converter receives digital coefficients assigned to the respective analog signals. A summation stage connected to output signals of the digital-analog converter integrates over a predetermined time period the output signals of the digital-analog converter representative of products of the analog signals and digital coefficients.

Abstract: An adaptive or self-adjusting corrector is provided for the correction or equalization of data signals formed with the primary value and a plurality of prior and subsequent oscillations. A plurality of delay members are provided for delaying the data signals. Members for multiplying the data signals by alterable coefficients are provided at outputs of each of the delay members. At least one adder connects with the coefficient members for summing up the multiplied data signals. Either a first coefficient member corresponding to the primary value of the data signal or a second coefficient member corresponding to a first subsequent oscillation of the data signal establish constant coefficients. Alternatively both the first and second coefficients may be made constant. Preferably the constant value is zero.

Abstract: An equalizer for correcting distorted, received data signals, i.e., partial-response signals, is described. The equalizer is of the type which uses a multi-stage shift register and an analog adder, the latter of which emits the corrected signal. In the transmission path between the output of the analog adder and the first stage of the shift register a second analog adder is interposed. An output of one of the succeeding stages of the shift register is connected directly to a second input of the second analog adder. The output of the second analog adder is coupled either directly or indirectly to the first stage of the shift register.