Abstract: According to one embodiment, an electronic circuit is described comprising an output circuit configured to output data elements, an input circuit configured to receive the data elements from the output circuit wherein the input circuit is clocked by a clock signal and receives the data elements in accordance with its clocking, a signaling circuit configured to, when the output circuit switches from the output of one data element to the output of a following data element, signal to interrupt the clocking of the input circuit and a controller configured to interrupt the clocking of the input circuit in response to the signaling.

Abstract: According to one embodiment, an electronic circuit is described comprising an output circuit configured to output data elements, an input circuit configured to receive the data elements from the output circuit wherein the input circuit is clocked by a clock signal and receives the data elements in accordance with its clocking, a signaling circuit configured to, when the output circuit switches from the output of one data element to the output of a following data element, signal to interrupt the clocking of the input circuit and a controller configured to interrupt the clocking of the input circuit in response to the signaling.

Abstract: Different exemplary embodiments provide a power supply apparatus for providing a voltage from an electromagnetic field, which apparatus has a conversion device which is set up to derive a voltage from a wirelessly received electromagnetic field, and a decoupling device which is coupled to the conversion device and has a first connection and a second connection, at each of which a supply voltage is provided, the decoupling device suppressing an effect of the circuits coupled to the first and second connections on the power supply apparatus.

Abstract: A system including a first device having a push-pull circuit configured to transmit a synchronization symbol; and a second device coupled to the first device by a single wire interface, and configured to, in response to receiving the synchronization symbol, transmit a data symbol to the first device while the push-pull circuit is in a tristate phase.

Abstract: A system including a first device having a push-pull circuit configured to transmit a synchronization symbol; and a second device coupled to the first device by a single wire interface, and configured to, in response to receiving the synchronization symbol, transmit a data symbol to the first device while the push-pull circuit is in a tristate phase.

Abstract: A contactless chip card may include: a first communication interface which is configured to receive a first signal by means of an electromagnetic field with a first frequency; a clock signal generating circuit which is coupled to the first communication interface and is configured to derive a clock signal from the first signal; a second communication interface which is coupled to the clock signal generating circuit and is configured to make available a signal transmission on the basis of the clock signal by means of an electromagnetic field with a second frequency, wherein the first frequency is different from the second frequency.

Abstract: Different exemplary embodiments provide a power supply apparatus for providing a voltage from an electromagnetic field, which apparatus has a conversion device which is set up to derive a voltage from a wirelessly received electromagnetic field, and a decoupling device which is coupled to the conversion device and has a first connection and a second connection, at each of which a supply voltage is provided, the decoupling device suppressing an effect of the circuits coupled to the first and second connections on the power supply apparatus.

Abstract: A signal processing circuit including a demodulator having an input for receiving a received signal which includes falling and rising signal edges, and an output for outputting a demodulated received signal which, with signal edges of the received signal, includes transitions from a first level to a second level or vice versa, wherein times of the transitions depend on steepnesses of the signal edges. Additionally, the circuit includes a signal generator having an input for receiving the demodulated received signal and coupled to the output of the demodulator, and an output for outputting a corrected demodulated received signal which includes transitions, the times of which relative to the times of the transitions of the demodulated received signal are set based on a reference signal to reduce influences of the steepnesses of the falling and rising signal edges in the corrected demodulated received signal relative to the demodulated received signal.

Abstract: Signal processing circuit including a demodulator that receives a receive signal with signal edges, and outputs a demodulated receive signal with transitions from a first level to a second level or vice versa at signal edges of the receive signal, wherein points of time of the transitions depend on the steepnesses of the signal edges. The circuit also includes an edge evaluator that receives the receive signal, and outputs an evaluation signal which includes information about the steepnesses of the signal edges. The circuit also includes a signal generator that receives the output of the demodulator, receives the output of the edge evaluator, and outputs a corrected demodulated receive signal with transitions whose points of time are set with regard to the points of time of the transitions of the demodulated receive signal based on the evaluation signal in order to reduce influences of different steepnesses of the signal edges.

Abstract: A circuit arrangement for matching a demodulator to operating conditions comprises a demodulator designed to demodulate an analog input signal to a demodulated signal. The demodulator is also designed to be driven by a control signal. The circuit arrangement further comprises a sensor which is designed to provide a sensor status signal, and a control unit to whose input side the sensor status signal is applied and which is designed to provide the control signal for the demodulator during operation.

Abstract: An interface apparatus having a first and a second buffer storage unit, the first buffer storage unit being associated with a first domain and the second buffer storage unit being associated with a second domain, and the buffer storage units being connected to one another for transmitting data. Each of the storage units is of two-stage design and respectively has a first and a second memory, the first and second buffer storage units are connected by unit of connections between the second memory in one buffer storage unit and the first memory in the other buffer storage unit, and data from one domain being written to the first memory and then to the second memory when a transmission operation is no longer pending between the domains.

Abstract: Signal processing circuit including a demodulator that receives a receive signal with signal edges, and outputs a demodulated receive signal with transitions from a first level to a second level or vice versa at signal edges of the receive signal, wherein points of time of the transitions depend on the steepnesses of the signal edges. The circuit also includes an edge evaluator that receives the receive signal, and outputs an evaluation signal which includes information about the steepnesses of the signal edges. The circuit also includes a signal generator that receives the output of the demodulator, receives the output of the edge evaluator, and outputs a corrected demodulated receive signal with transitions whose points of time are set with regard to the points of time of the transitions of the demodulated receive signal based on the evaluation signal in order to reduce influences of different steepnesses of the signal edges.

Abstract: A signal processing circuit including a demodulator having an input for receiving a received signal which includes falling and rising signal edges, and an output for outputting a demodulated received signal which, with signal edges of the received signal, includes transitions from a first level to a second level or vice versa, wherein times of the transitions depend on steepnesses of the signal edges. Additionally, the circuit includes a signal generator having an input for receiving the demodulated received signal and coupled to the output of the demodulator, and an output for outputting a corrected demodulated received signal which includes transitions, the times of which relative to the times of the transitions of the demodulated received signal are set based on a reference signal to reduce influences of the steepnesses of the falling and rising signal edges in the corrected demodulated received signal relative to the demodulated received signal.

Abstract: A circuit arrangement for matching a demodulator to operating conditions comprises a demodulator designed to demodulate an analog input signal to a demodulated signal. The demodulator is also designed to be driven by a control signal. The circuit arrangement further comprises a sensor which is designed to provide a sensor status signal, and a control unit to whose input side the sensor status signal is applied and which is designed to provide the control signal for the demodulator during operation.

Abstract: An interface apparatus having a first and a second buffer storage unit, the first buffer storage unit being associated with a first domain and the second buffer storage unit being associated with a second domain, and the buffer storage units being connected to one another for transmitting data. Each of the storage units is of two-stage design and respectively has a first and a second memory, the first and second buffer storage units are connected by unit of connections between the second memory in one buffer storage unit and the first memory in the other buffer storage unit, and data from one domain being written to the first memory and then to the second memory when a transmission operation is no longer pending between the domains.