Patents by Inventor Helmut Oefner
Helmut Oefner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230395394Abstract: A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.Type: ApplicationFiled: August 22, 2023Publication date: December 7, 2023Inventors: Hans-Joachim Schulze, Alexander Breymesser, Bernhard Goller, Matthias Kuenle, Helmut Oefner, Francisco Javier Santos Rodriguez, Stephan Voss
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Patent number: 11742215Abstract: A method of forming a semiconductor device, including forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate, increasing the porosity of the first semiconductor layer, first annealing the first semiconductor layer at a temperature of at least 1050° C., forming a second semiconductor layer on the first semiconductor layer and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer.Type: GrantFiled: July 28, 2021Date of Patent: August 29, 2023Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Alexander Breymesser, Bernhard Goller, Matthias Kuenle, Helmut Oefner, Francisco Javier Santos Rodriguez, Stephan Voss
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Publication number: 20220042204Abstract: A method of manufacturing CZ silicon wafers is proposed. The method includes extracting a CZ silicon ingot over an extraction time period from a silicon melt including dopants being predominantly n-type. The method further includes introducing boron into the CZ silicon ingot over at least part of the extraction time period by controlling a boron supply to the silicon melt by a boron source. The method further includes determining a specific resistivity, a boron concentration, and a carbon concentration along a crystal axis of the CZ silicon ingot. The method further includes slicing the CZ silicon ingot or a section of the CZ silicon ingot into CZ silicon wafers. The method further includes determining at least two groups of the CZ silicon wafers depending on at least two of the specific resistivity, the boron concentration, and the carbon concentration.Type: ApplicationFiled: July 30, 2021Publication date: February 10, 2022Inventors: Hans-Joachim Schulze, Helmut Oefner
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Publication number: 20220037165Abstract: A method of forming a semiconductor device, including forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate, increasing the porosity of the first semiconductor layer, first annealing the first semiconductor layer at a temperature of at least 1050° C., forming a second semiconductor layer on the first semiconductor layer and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer.Type: ApplicationFiled: July 28, 2021Publication date: February 3, 2022Inventors: Hans-Joachim Schulze, Alexander Breymesser, Bernhard Goller, Matthias Kuenle, Helmut Oefner, Francisco Javier Santos Rodriguez, Stephan Voss
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Patent number: 10957767Abstract: A method of manufacturing is provided that includes providing an n-type silicon wafer, the n-type silicon wafer including n-type dopants partially compensated 20% to 80% by p-type dopants, where a net n-type doping concentration of the n-type silicon wafer is in a range from 1×1013 cm?3 to 1×1015 cm?3; forming hydrogen related donors in the n-type silicon wafer by irradiating the n-type silicon wafer with protons; and annealing the n-type silicon wafer after forming the hydrogen related donors.Type: GrantFiled: January 27, 2020Date of Patent: March 23, 2021Inventors: Nico Caspary, Helmut Oefner, Hans-Joachim Schulze
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Patent number: 10837120Abstract: One example describes a method of manufacturing Czochralski (CZ) silicon wafers. The method includes slicing an n-type CZ silicon ingot to form a plurality of CZ silicon wafers, determining a boron concentration of each CZ silicon wafer, dividing the CZ silicon wafers into sub-groups based on the boron concentration, wherein an average value of the boron concentration differs among the sub-groups, and labeling each sub-group of CZ silicon wafers with a different label which is indicative of the boron concentration.Type: GrantFiled: March 26, 2020Date of Patent: November 17, 2020Assignee: Infineon Technologies AGInventors: Johannes Freund, Thomas Wuebben, Helmut Oefner, Hans-Joachim Schulze
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Patent number: 10724149Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.Type: GrantFiled: March 29, 2019Date of Patent: July 28, 2020Assignee: Infineon Technologies AGInventors: Johannes Freund, Thomas Wuebben, Helmut Oefner, Hans-Joachim Schulze
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Publication number: 20200224326Abstract: One example describes a method of manufacturing Czochralski (CZ) silicon wafers. The method includes slicing an n-type CZ silicon ingot to form a plurality of CZ silicon wafers, determining a boron concentration of each CZ silicon wafer, dividing the CZ silicon wafers into sub-groups based on the boron concentration, wherein an average value of the boron concentration differs among the sub-groups, and labeling each sub-group of CZ silicon wafers with a different label which is indicative of the boron concentration.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Applicant: Infineon Technologies AGInventors: Johannes Freund, Thomas Wuebben, Helmut Oefner, Hans-Joachim Schulze
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Publication number: 20200161424Abstract: A method of manufacturing is provided that includes providing an n-type silicon wafer, the n-type silicon wafer including n-type dopants partially compensated 20% to 80% by p-type dopants, where a net n-type doping concentration of the n-type silicon wafer is in a range from 1×1013 cm?3 to 1×1015 cm?3; forming hydrogen related donors in the n-type silicon wafer by irradiating the n-type silicon wafer with protons; and annealing the n-type silicon wafer after forming the hydrogen related donors.Type: ApplicationFiled: January 27, 2020Publication date: May 21, 2020Applicant: Infineon Technologies AGInventors: Nico CASPARY, Helmut OEFNER, Hans-Joachim SCHULZE
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Patent number: 10566424Abstract: A method of manufacturing a silicon wafer is provided that includes extracting an n-type silicon ingot over an extraction time period from the a silicon melt comprising n-type dopants; adding p-type dopants to the silicon melt over at least part of the extraction time period, thereby compensating an n-type doping in the n-type silicon ingot by 10% to 80%; slicing the silicon ingot; forming hydrogen related donors in the silicon wafer by irradiating the silicon wafer with protons; and annealing the silicon wafer subsequent to the forming of the hydrogen related donors in the silicon wafer.Type: GrantFiled: November 22, 2017Date of Patent: February 18, 2020Assignee: Infineon Technologies AGInventors: Nico Caspary, Helmut Oefner, Hans-Joachim Schulze
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Patent number: 10566198Abstract: A first dose of first dopants is introduced into a semiconductor body having a first surface. A thickness of the semiconductor body is increased by forming a first semiconductor layer on the first surface of the semiconductor body. While forming the first semiconductor layer a final dose of doping in the first semiconductor layer is predominantly set by introducing at least 20% of the first dopants from the semiconductor body into the first semiconductor layer.Type: GrantFiled: September 19, 2018Date of Patent: February 18, 2020Assignee: INFINEON TECHNOLOGIES AGInventors: Hans-Joachim Schulze, Johannes Baumgartl, Helmut Oefner
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Patent number: 10529838Abstract: A semiconductor device includes at least one transistor structure. The at least one transistor structure includes an emitter or source terminal, and a collector or drain terminal. A carbon concentration within a semiconductor substrate region located between the emitter or source terminal and the collector or drain terminal varies between the emitter or source terminal and the collector or drain terminal.Type: GrantFiled: December 4, 2017Date of Patent: January 7, 2020Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Moriz Jelinek, Johannes Laven, Helmut Oefner, Werner Schustereder
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Publication number: 20190249330Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.Type: ApplicationFiled: March 29, 2019Publication date: August 15, 2019Applicant: Infineon Technologies AGInventors: Johannes Freund, Thomas Wuebben, Helmut Oefner, Hans-Joachim Schulze
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Patent number: 10317338Abstract: A method of determining the carbon content in a silicon sample may include: generating electrically active polyatomic complexes within the silicon sample. Each polyatomic complex may include at least one carbon atom. The method may further include: determining a quantity indicative of the content of the generated polyatomic complexes in the silicon sample, and determining the carbon content in the silicon sample from the determined quantity.Type: GrantFiled: September 27, 2017Date of Patent: June 11, 2019Assignee: INFINEON TECHNOLOGIES AGInventors: Naveen Goud Ganagona, Moriz Jelinek, Helmut Oefner, Hans-Joachim Schulze, Werner Schustereder
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Patent number: 10319599Abstract: A method of planarizing a roughened surface of a SiC substrate includes: forming a sacrificial material on the roughened surface of the SiC substrate, the sacrificial material having a density between 35% and 120% of the density of the SiC substrate; implanting ions through the sacrificial material and into the roughened surface of the SiC substrate to form an amorphous region in the SiC substrate; and removing the sacrificial material and the amorphous region of the SiC substrate by wet etching.Type: GrantFiled: May 31, 2017Date of Patent: June 11, 2019Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Helmut Oefner, Roland Rupp
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Patent number: 10273597Abstract: In accordance with a method of manufacturing CZ silicon wafers, a parameter of at least two of the CZ silicon wafers is measured. A group of the CZ silicon wafers falling within a tolerance of a target specification is determined. The group of the CZ silicon wafers is divided into sub-groups taking into account the measured parameter. An average value of the parameter of the CZ silicon wafers of each sub-group differs among the sub-groups, and a tolerance of the parameter of the CZ silicon wafers of each sub-group is smaller than a tolerance of the parameter of the target specification. A labeling configured to distinguish between the CZ silicon wafers of different sub-groups is prepared. The CZ silicon wafers falling within the tolerance of the target specification are packaged.Type: GrantFiled: June 29, 2017Date of Patent: April 30, 2019Assignee: Infineon Technologies AGInventors: Johannes Freund, Thomas Wuebben, Helmut Oefner, Hans-Joachim Schulze
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Publication number: 20190088482Abstract: A first dose of first dopants is introduced into a semiconductor body having a first surface. A thickness of the semiconductor body is increased by forming a first semiconductor layer on the first surface of the semiconductor body. While forming the first semiconductor layer a final dose of doping in the first semiconductor layer is predominantly set by introducing at least 20% of the first dopants from the semiconductor body into the first semiconductor layer.Type: ApplicationFiled: September 19, 2018Publication date: March 21, 2019Inventors: Hans-Joachim Schulze, Johannes Baumgartl, Helmut Oefner
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Publication number: 20180350612Abstract: A method of planarizing a roughened surface of a SiC substrate includes: forming a sacrificial material on the roughened surface of the SiC substrate, the sacrificial material having a density between 35% and 120% of the density of the SiC substrate; implanting ions through the sacrificial material and into the roughened surface of the SiC substrate to form an amorphous region in the SiC substrate; and removing the sacrificial material and the amorphous region of the SiC substrate by wet etching.Type: ApplicationFiled: May 31, 2017Publication date: December 6, 2018Inventors: Hans-Joachim Schulze, Helmut Oefner, Roland Rupp
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Patent number: 10026816Abstract: A semiconductor wafer includes first and second main surfaces opposite to each other along a vertical direction, and a side surface encircling the semiconductor wafer. A lateral distance perpendicular to the vertical direction between the side surface and a center of the semiconductor wafer includes first and second parts. The first part extends from the side surface to the second part and the second part extends from the first part to the center. An average concentration of at least one of nitrogen and oxygen in the first part is greater than 5×1014 cm?3 and exceeds an average concentration of the at least one of nitrogen and oxygen in the second part by more than 20% of the average concentration of the at least one of nitrogen and oxygen in the second part.Type: GrantFiled: March 30, 2015Date of Patent: July 17, 2018Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Helmut Oefner
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Patent number: 10014400Abstract: A semiconductor device includes: a semiconductor substrate having a first side, a second side opposite the first side, and a thickness; at least one semiconductor component integrated in the semiconductor substrate; a first metallization at the first side of the semiconductor substrate; and a second metallization at the second side of the semiconductor substrate. The semiconductor substrate has an oxygen concentration along a thickness line of the semiconductor substrate which has a global maximum at a position of 20% to 80% of the thickness relative to the first side. The global maximum is at least 2-times larger than the oxygen concentrations at each of the first side and the second side of the semiconductor substrate.Type: GrantFiled: July 14, 2017Date of Patent: July 3, 2018Assignee: Infineon Technologies AGInventors: Helmut Oefner, Nico Caspary, Mohammad Momeni, Reinhard Ploss, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze