Patents by Inventor Helmut Rinck
Helmut Rinck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240222470Abstract: A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.Type: ApplicationFiled: January 31, 2024Publication date: July 4, 2024Inventors: Sebastian Meier, Helmut Rinck, Mike Mittelstaedt
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Patent number: 11929423Abstract: A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.Type: GrantFiled: June 15, 2021Date of Patent: March 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sebastian Meier, Helmut Rinck, Mike Mittelstaedt
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Publication number: 20230253211Abstract: There is provided a method of patterning platinum on a substrate. A platinum layer is deposited on the substrate, and a patterned photoresist layer is formed over the platinum layer leaving partly exposed regions of the platinum layer. An aluminum layer is deposited over the partly exposed regions of the platinum layer. An alloy is formed of aluminum with platinum from the partly exposed regions. The platinum aluminum alloy is etched away leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate. In an embodiment, a thin hard mask layer is deposited on the platinum layer on the semiconductor substrate before the patterned photoresist layer is formed.Type: ApplicationFiled: April 13, 2023Publication date: August 10, 2023Inventors: Sebastian Meier, Helmut Rinck
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Publication number: 20230184713Abstract: In some examples, an integrated circuit comprises: a semiconductor die including a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a metallization structure encapsulated in the dielectric layer, in which the semiconductor substrate includes a transistor having a first current terminal, a second current terminal, and a channel region between the first and second current terminals, and the dielectric layer has a sensing side facing away from the semiconductor substrate; an insulation layer on the sensing side; a sensor terminal on the sensing side and over the channel region; and a restriction structure including an opening and a rigid silicon-based fluidic structure, in which the silicon-based fluidic structure is on the sensing side and encapsulates a fluid cavity on the sensing side, the sensor terminal is in the fluid cavity, and the restriction structure is configured to transport a fluid by microfluidic diffusion.Type: ApplicationFiled: December 14, 2022Publication date: June 15, 2023Applicant: Texas Instruments IncorporatedInventors: Sebastian Meier, Ernst Muellner, Helmut Rinck, Scott Summerfelt, Tobias Fritz, Baher Haroun
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Publication number: 20230187390Abstract: In one example, a semiconductor die comprises: a semiconductor substrate having a circuit formed therein; one or more metal layers on the semiconductor substrate, the one or more metal layers coupled to the circuit; a metal interface structure on the one or more metal layers, in which the metal interface structure has opposite first and second surfaces, and the first surface faces the one or more metal layers; and a dissolvable metal layer on the second surface.Type: ApplicationFiled: September 30, 2022Publication date: June 15, 2023Inventors: Sebastian MEIER, Bernhard ZIEGLTRUM, Helmut RINCK
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Patent number: 11658034Abstract: There is provided a method of patterning platinum on a substrate. A platinum layer is deposited on the substrate, and a patterned photoresist layer is formed over the platinum layer leaving partly exposed regions of the platinum layer. An aluminum layer is deposited over the partly exposed regions of the platinum layer. An alloy is formed of aluminum with platinum from the partly exposed regions. The platinum aluminum alloy is etched away leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate. In an embodiment, a thin hard mask layer is deposited on the platinum layer on the semiconductor substrate before the patterned photoresist layer is formed.Type: GrantFiled: April 20, 2021Date of Patent: May 23, 2023Assignee: Texas Instruments IncorporatedInventors: Sebastian Meier, Helmut Rinck
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Publication number: 20210313179Abstract: A microelectronic device includes a substrate a platinum-containing layer over the substrate. The platinum-containing layer includes a first segment and a second segment adjacent to the first segment, and has a first surface and a second surface opposite the first surface closer to the substrate than the first surface. A first spacing between the first segment and the second segment at the first surface is greater than a second spacing between the first segment and the second segment at the second surface. A width of the first segment along the first surface is less than twice a thickness of the first segment, and the second spacing is less than twice the thickness of the first segment.Type: ApplicationFiled: June 15, 2021Publication date: October 7, 2021Inventors: Sebastian Meier, Helmut Rinck, Mike Mittelstaedt
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Publication number: 20210242029Abstract: There is provided a method of patterning platinum on a substrate. A platinum layer is deposited on the substrate, and a patterned photoresist layer is formed over the platinum layer leaving partly exposed regions of the platinum layer. An aluminum layer is deposited over the partly exposed regions of the platinum layer. An alloy is formed of aluminum with platinum from the partly exposed regions. The platinum aluminum alloy is etched away leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate. In an embodiment, a thin hard mask layer is deposited on the platinum layer on the semiconductor substrate before the patterned photoresist layer is formed.Type: ApplicationFiled: April 20, 2021Publication date: August 5, 2021Inventors: Sebastian Meier, Helmut Rinck
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Patent number: 11069530Abstract: A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.Type: GrantFiled: November 19, 2019Date of Patent: July 20, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sebastian Meier, Helmut Rinck, Mike Mittelstaedt
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Patent number: 11011381Abstract: There is provided a method of patterning platinum on a substrate. A platinum layer is deposited on the substrate, and a patterned photoresist layer is formed over the platinum layer leaving partly exposed regions of the platinum layer. An aluminum layer is deposited over the partly exposed regions of the platinum layer. An alloy is formed of aluminum with platinum from the partly exposed regions. The platinum aluminum alloy is etched away leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate. In an embodiment, a thin hard mask layer is deposited on the platinum layer on the semiconductor substrate before the patterned photoresist layer is formed.Type: GrantFiled: July 26, 2019Date of Patent: May 18, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sebastian Meier, Helmut Rinck
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Patent number: 10714439Abstract: A system and method for bonding an electrically conductive mechanical interconnector (e.g., a bonding wire, solder, etc.) to an electrical contact (e.g., contact pad, termination on a printed circuit board (PCB), etc.) made from an electrically conductive metal (e.g., aluminum) on an electronic device (e.g., integrated circuit (IC), die, wafer, PCB, etc.) is provided. The electrical contact is chemically coated with a metal (e.g., cobalt) that provides a protective barrier between the mechanical interconnector and the electrical contact. The protective barrier provides a diffusion barrier to inhibit galvanic corrosion (i.e. ion diffusion) between the mechanical interconnector and the electrical contact.Type: GrantFiled: August 21, 2018Date of Patent: July 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Nazila Dadvand, Helmut Rinck
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Publication number: 20200083050Abstract: A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.Type: ApplicationFiled: November 19, 2019Publication date: March 12, 2020Inventors: Sebastian Meier, Helmut Rinck, Mike Mittelstaedt
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Publication number: 20200035500Abstract: There is provided a method of patterning platinum on a substrate. A platinum layer is deposited on the substrate, and a patterned photoresist layer is formed over the platinum layer leaving partly exposed regions of the platinum layer. An aluminum layer is deposited over the partly exposed regions of the platinum layer. An alloy is formed of aluminum with platinum from the partly exposed regions. The platinum aluminum alloy is etched away leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate. In an embodiment, a thin hard mask layer is deposited on the platinum layer on the semiconductor substrate before the patterned photoresist layer is formed.Type: ApplicationFiled: July 26, 2019Publication date: January 30, 2020Inventors: Sebastian Meier, Helmut Rinck
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Patent number: 10504733Abstract: A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.Type: GrantFiled: September 25, 2017Date of Patent: December 10, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sebastian Meier, Helmut Rinck, Mike Mittelstaedt
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Patent number: 10297497Abstract: In accordance with at least one embodiment of the disclosure, a method of patterning platinum on a substrate is disclosed. In an embodiment, an adhesive layer is deposited over the substrate, a sacrificial layer is deposited over the adhesive layer, and a patterned photoresist layer is formed over the sacrificial layer. Then, the sacrificial layer is patterned utilizing the photoresist layer as a mask such that at least a portion of the adhesive layer is exposed. Subsequently, the top and sidewall surfaces of the patterned sacrificial layer and the first portion of the adhesive layer are covered by a platinum layer. Finally, the sacrificial layer and a portion of the platinum layer covering the top and sidewall surfaces of the sacrificial layer are etched, thereby leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate.Type: GrantFiled: July 24, 2017Date of Patent: May 21, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sebastian Meier, Helmut Rinck, Kai-Alexander Schachtschneider, Fromund Metz, Mario Schmidpeter, Javier Gustavo Moreira
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Publication number: 20190109104Abstract: A system and method for bonding an electrically conductive mechanical interconnector (e.g., a bonding wire, solder, etc.) to an electrical contact (e.g., contact pad, termination on a printed circuit board (PCB), etc.) made from an electrically conductive metal (e.g., aluminum) on an electronic device (e.g., integrated circuit (IC), die, wafer, PCB, etc.) is provided. The electrical contact is chemically coated with a metal (e.g., cobalt) that provides a protective barrier between the mechanical interconnector and the electrical contact. The protective barrier provides a diffusion barrier to inhibit galvanic corrosion (i.e. ion diffusion) between the mechanical interconnector and the electrical contact.Type: ApplicationFiled: August 21, 2018Publication date: April 11, 2019Inventors: NAZILLA DADVAND, HELMUT RINCK
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Publication number: 20180218993Abstract: A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads includes a metal bond pad area. A cobalt including connection layer is deposited directly on the metal bond pad area. The cobalt including connection layer is patterned to provide a cobalt bond pad surface for the plurality of bond pads, and a solder material is formed on the cobalt bond pad surface.Type: ApplicationFiled: March 27, 2018Publication date: August 2, 2018Inventors: HELMUT RINCK, GERNOT BAUER, ROBERT ZRILE, KAI-ALEXANDER SCHACHTSCHNEIDER, MICHAEL OTTE, HARALD WIESNER
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Publication number: 20180204734Abstract: A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.Type: ApplicationFiled: September 25, 2017Publication date: July 19, 2018Applicant: Texas Instruments IncorporatedInventors: Sebastian Meier, Helmut Rinck, Mike Mittelstaedt
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Publication number: 20180204767Abstract: In accordance with at least one embodiment of the disclosure, a method of patterning platinum on a substrate is disclosed. In an embodiment, an adhesive layer is deposited over the substrate, a sacrificial layer is deposited over the adhesive layer, and a patterned photoresist layer is formed over the sacrificial layer. Then, the sacrificial layer is patterned utilizing the photoresist layer as a mask such that at least a portion of the adhesive layer is exposed. Subsequently, the top and sidewall surfaces of the patterned sacrificial layer and the first portion of the adhesive layer are covered by a platinum layer. Finally, the sacrificial layer and a portion of the platinum layer covering the top and sidewall surfaces of the sacrificial layer are etched, thereby leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate.Type: ApplicationFiled: July 24, 2017Publication date: July 19, 2018Inventors: Sebastian MEIER, Helmut RINCK, Kai-Alexander SCHACHTSCHNEIDER, Fromund METZ, Mario SCHMIDPETER, Javier Gustavo MOREIRA
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Patent number: 9960135Abstract: A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads includes a metal bond pad area. A cobalt including connection layer is deposited directly on the metal bond pad area. The cobalt including connection layer is patterned to provide a cobalt bond pad surface for the plurality of bond pads, and a solder material is formed on the cobalt bond pad surface.Type: GrantFiled: March 23, 2015Date of Patent: May 1, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Helmut Rinck, Gernot Bauer, Robert Zrile, Kai-Alexander Schachtschneider, Michael Otte, Harald Wiesner